LT3922EUFD datasheet(21/30 Pages) LINEAR

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LT3922

3922f

For more information www.linear.com/LT3922

applicaTions inForMaTion

Figure 12. OVLO Threshold and Hysteresis Voltages

Figure 13. EN/UVLO–OVLO Threshold and Hysteresis Voltages

additional hysteresis through the external resistor as the

EN/UVLO pin sinks 2µA current when the EN/UVLO pin

voltage is below the threshold.

On the other hand, the VIN overvoltage lockout (OVLO)

threshold can be accurately set by the external resistor

divider as well. Figure 12 illustrates how to set the rising

OVLO threshold in LT3922. The internal hysteresis of the

OVLO pin is 50mV.

The exposed pad on the bottom of the package must be

soldered to a ground plane. Vias placed directly under the

package are necessary to dissipate heat.

Designing the Printed Circuit Board (PCB)

The output capacitors COUT1 and COUT2 of the LT3922

bypass large switched currents from VOUT to GND (see

Figure 5). The loops travelled by these currents should

be made small as possible to these pins. These output

capacitors, along with the inductor and the input capaci-

tors, should be placed on the same side of the PCB, and

their connections should be made on that layer.

Create a Kelvin ground network by keeping the ground

connection for all of the other components separate.

It should only join the ground for the input and output

capacitors and the return path for the LED current at the

exposed pad.

There are a few other aspects of the board design that

improve performance. An unbroken ground plane on

the second layer dissipates heat, but also reduces noise.

Likewise minimizing the area of the SW and BST nodes

reduces noise. The traces for FB and VC should be kept

short to lessen the susceptibility to noise of these high-

impedance nodes. Matched Kelvin connections from the

external current sense resistor to the ISP and ISN pins

are essential for current regulation accuracy. The 2.2μF

INTVCC and 1µF VREF capacitors as well as the 100nF BST

capacitor should be placed as closely as possible to their

respective pins. Use bypass capacitors for the DC input

nodes such as VIN, CTRL, and PWM (for internal PWM) to

reduce noise. Keep the RT and RP nodes small and away

from noisy signals. Finally, a diode with anode connected

to ground and cathode to the drain of the PWMTG MOS-

FET can protect that device from overvoltage caused by

excessive inductance in the LED string. Please refer to the

demo board layout of the LT3922 for more information.

Both EN/UVLO and OVLO can be set precisely using a

single resistor string consisting of three series resistors.

Figure 13 shows the resistor string and the threshold and

hysteresis voltages for EN/UVLO and OVLO.

Tie EN/UVLO to VIN and tie OVLO to GND if they are not

used. Do not leave these pins open.

Planning for Thermal Shutdown

TheLT3922automaticallystopsswitchingwhentheinternal

temperatureistoohigh.Thetemperaturelimitisguaranteed

to be higher than the operational temperature of the part.

During thermal shutdown, all switching is terminated, SS

is forced low, and the LEDs are disconnected through the

PWMTG driver.

LT3922

3922 F12

OVLO

VIN

RISING THRESHOLD

VIN(OVLO) =1.205V • 1+









FALLING HYSTERESIS

VHYST(OVLO) =50mV • 1+









VIN(UVLO) =1.33V • 1+

R6+R7









VHYST(UVLO) =25mV • 1+

R6+R7









+R5•2µA

VIN(OVLO) =1.205V • 1+

R5+R6









VHYST(OVLO) =50mV • 1+

R5+R6









LT3922

3922 F13

EN/UVLO

VIN

OVLO

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