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ST92185B - A/D CONVERTER (A/D)

7.7 A/D CONVERTER (A/D)

7.7.1 Introduction

The 8 bit Analog to Digital Converter uses a fully

differential analog configuration for the best noise

immunity and precision performance. The analog

voltage references of the converter are connected

to the internal AVDD & AVSS analog supply pins of

the chip if they are available, otherwise to the ordi-

nary VDD and VSS supply pins of the chip. The

guaranteed accuracy depends on the device (see

Electrical Characteristics). A fast Sample/Hold al-

lows quick signal sampling for minimum warping

effect and conversion error.

7.7.2 Main Features

8-bit resolution A/D Converter

Single Conversion Time (including Sampling

Time):

– 138 internal system clock periods in slow

mode (~5.6 µs @25Mhz internal system

clock);

– 78 INTCLK periods in fast mode (~6.5 µs @

12MHZ internal system clock)

Sample/Hold: Tsample=

– 84 INTCLK periods in slow mode (~3.4 µs

@25Mhz internal system clock)

– 48 INTCLK periods in fast mode (~4 µs

@12Mhz internal system clock)

Up to 4 Analog Inputs (the number of inputs is

device dependent, see device pinout)

Single/Continuous Conversion Mode

External/Internal

source

Trigger

(Alternate

synchronization)

Power Down mode (Zero Power Consumption)

1 Control Logic Register

1 Data Register

7.7.3 General Description

Depending on the device, up to 8 analog inputs

can be selected by software.

Different conversion modes are provided: single,

continuous, or triggered. The continuous mode

performs a continuous conversion flow of the se-

lected channel, while in the single mode the se-

lected channel is converted once and then the log-

ic waits for a new hardware or software restart.

A data register (ADDTR) is available, mapped in

page 62, allowing data storage (in single or contin-

uous mode).

The start conversion event can be managed by

software, writing the START/STOP bit of the Con-

trol Logic Register or by hardware using either:

– An external signal on the EXTRG triggered input

(negative edge sensitive) connected as an Alter-

nate Function to an I/O port bit

– An On Chip Event generated by another periph-

eral, such as the MFT (Multifunction Timer).

Figure 97. A/D Converter Block Diagram

SUCCESSIVE

APPROXIMATION

ANALOG

MUX

DATA

CONTROL LOGIC

S/H

Ain1

Ainx

INTRG

(On Chip Event)

Ain0

EXTRG

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