ST92185B datasheet(156/178 Pages) STMICROELECTRONICS

156 / 178 page

156/178

ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)

7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS)

7.8.1 Description

The on-chip Voltage Synthesis (VS) converter al-

lows the generation of a tuning reference voltage

in a TV set application. The peripheral is com-

posed of a 14-bit counter that allows the conver-

sion of the digital content in a tuning voltage, avail-

able at the VS output pin, by using PWM (Pulse

Width Modulation) and BRM (Bit Rate Modulation)

techniques. The 14-bit counter gives 16384 steps

which allow a resolution of approximately 2 mV

over a tuning voltage of 32 V. This corresponds to

a tuning resolution of about 40 KHz per step in

UHF band (the actual value will depend on the

characteristics of the tuner).

The tuning word consists of a 14-bit word con-

tained in the registers VSDR1 (R254) and VSDR2

(R255) both located in page 59.

Coarse tuning (PWM) is performed using the sev-

en most significant bits. Fine tuning (BRM) is per-

formed using the the seven least significant bits.

With all “0”s loaded, the output is 0. As the tuning

voltage increases from all “0”s, the number of puls-

es in one period increases to 128 with all pulses

being the same width. For values larger than 128,

the PWM takes over and the number of pulses in

one period remains constant at 128, but the width

changes. At the other end of the scale, when al-

most all “1”s are loaded, the pulses will start to link

together and the number of pulses will decrease.

When all “1”s are loaded, the output will be almost

100% high but will have a low pulse (1/16384 of

the high pulse).

7.8.2 Output Waveforms

Included inside the VS are the register latches, a

reference counter, PWM and BRM control circuit-

ry. The clock for the 14-bit reference counter is de-

rived from the main system clock (referred to as

INTCLK) after a division by 4. For example, using

an internal 12 MHz on-chip clock (see Timing &

Clock Controller chapter) leads to a 3 MHz input

for the VS counter.

From the point of view of the circuit, the seven

most significant bits control the coarse tuning,

while the seven least significant bits control the

fine tuning. From the application and software

point of view, the 14 bits can be considered as one

binary number.

As already mentioned the coarse tuning consists

of a PWM signal with 128 steps: we can consider

the fine tuning to cover 128 coarse tuning cycles.

The VS Tuning Converter is implemented with 2

separate outputs (VSO1 and VSO2) that can drive

2 separate Alternate Function outputs of 2 stand-

ard I/O port bits. A control bit allows you to choose

which output is activated (only one output can be

activated at a time).

When a VS output is not selected because the VS

is disabled or because the second output is select-

ed, it stays at a logical “one” level, allowing you to

use the corresponding I/O port bit either as a nor-

mal I/O port bit or for a possible second Alternate

Function output.

A second control bit allows the VS function to be

started (or stopped) by software.

ST92185B Datasheet(PDF) 156 Page - STMicroelectronics

ST92185B Datasheet(HTML) 156 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL