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MR27T802F Datasheet(PDF) 2 Page - LAPIS Semiconductor Co., Ltd. |
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MR27T802F Datasheet(HTML) 2 Page - LAPIS Semiconductor Co., Ltd. |
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2 / 9 page ![]() FEDR27T802F-002-06 MR27T802F / P2ROM BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 CE# BYTE# OE# CE OE × 8/× 16 Switch D0 D2 D4 D6 D8 D10 D12 D14 D1 D3 D5 D7 D9 D11 D13 D15 Memory Cell Matrix 512k × 16-Bit or 1M × 8-Bit Multiplexer Output Buffer In 8-bit output mode, these pins are placed in a high-Z state and pin D15 functions as the A-1 address pin. A–1 PIN DESCRIPTIONS Pin name Functions D15 / A–1 Data output / Address input A0 to A18 Address inputs D0 to D14 Data outputs CE# Chip enable input OE# Output enable input BYTE# Word / Byte select input VCC Power supply voltage VSS Ground NC No connect 2/9 |
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