PCA9518 datasheet(8/12 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9518

Expandable 5-channel I2C hub

2004 Sep 29

AC ELECTRICAL CHARACTERISTICS1

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS3

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPHLs

Propagation delay

SDA to SDAn or SCL to SCLn

Waveform 1; Note 2

105

202

389

tPLHs

Propagation delay

SDA to SDAn or SCL to SCLn

Waveform 1; Note 3

110

259

265

tPHLE1s

Propagation delay

EXPSDA1 to SDA or EXPSCL1 to SCL

Waveform 1

109

193

327

tPLHE1s

Propagation delay

EXPSDA1 to SDA or EXPSCL1 to SCL

Waveform 1

130

153

179

tPLHE2s

Propagation delay

EXPSDA2 to SDA or EXPSCL2 to SCL

Waveform 1

160

234

279

tTHLs

Transition time, SDA/SCL

Waveform 1

110

187

tTLHs

Transition time, SDA/SCL

Waveform 1

—

0.85 RC

—

tSET

Enable to Start condition

300

—

tHOLD

Enable after Stop condition

300

—

NOTES:

1. The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are only

sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific numerical value can only be given for

fixed RC time constants.

2. The SDA HIGH to LOW propagation delay, tPLHs, includes the fall time from VCC to 0.5 VCC of the EXPSDA1 or EXPSCL1 pins and the SDA

or SCL fall time from the quiescent HIGH (usually VCC) to below 0.3 VCC. The SDA and SCL outputs have edge rate control circuits included

which make the fall time almost independent of load capacitance.

3. The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5 VCC for the EXPSDA1 or

EXPSCL2, the rise time constant for the quiescent LOW to 0.5 VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from the

quiescent external driven LOW to 0.7 VCC for the SDA or SCL output. All of these rise times are RC time constants determined by the

external R and total C for the various nodes.

AC WAVEFORMS

SW01089

0.7 VCC

0.4 V

tTLHs

tTHLs

tPHLs

tTHLs

tPHLs

EFFECTIVE

STRETCH

tPLHs

tPLHE1s

tPLHE2s

tPLHs

0.3 VCC

0.4 V

0.3 VCC

0.7 VCC

0.5 VCC

0.7 VCC

0.3 VCC

0.52 V

INPUT

SDA

OR SCL

EXPSDA1

EXPSCL1

EXPSDA2

EXPSCL2

OUTPUT

SDA

OR SCL

Waveform 1.

TEST CIRCUIT

DEFINITIONS

RL = Load resistor; 1.1 kΩ for I2C and 500 Ω for EXP.

CL = Load capacitance includes jig and probe capacitance;

100 pF for I2C and 100 pF for EXP

RT = Termination resistance should be equal to ZOUT of

pulse generators.

PULSE

GENERATOR

VIN

D.U.T.

VOUT

VCC

Test circuit for open-drain outputs

SW01088

VCC

Figure 6. Test circuit

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