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MT9072AB Datasheet(PDF) 239 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 239 Page - Zarlink Semiconductor Inc |
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239 / 275 page  MT9072 Data Sheet 239 Zarlink Semiconductor Inc. Figure 25 - 8 E1 Links with ATM IMA with Asynchronous ST-BUS Mode RPOS RNEG E2i TPOS TNEG T2o DSTo RxDLC RxBF DSTi CKi FPi Framer 1/8 RPOS RNEG RCLK TPOS TNEG TCLK LIU 1/8 RT RR TT TR Transmit xfmr LINE 1 Receive xfmr Notes: Framer 1-8, 1 of MT9072 LIU 1-8, 8 of Generic LIU PLL, 1 of MT9042 IMA - Framer elastic buffer is bypassed at DSTo. - LIU Transmit JA and PLL are enabled. - Transmit and receive paths may be asynchronous with each other. RPOS RNEG RCLK TPOS TNEG TCLK LIU 8/8 RT RR TT TR Transmit xfmr LINE 8 Receive xfmr LINES 2 to 7 Framers 2 to 7 DSTo RxDLC RxBF DSTi CKi FPi LIU’s 2 to 7 DSTi0 RxCK0 RxSYNC0 DSTo0 TxCK0 TxSYNC0 DSTi 1-6 RxCK1-6 RxSYNC1-6 DSTo1-6 TxCK1-6 TxSYNC1-6 DSTi7 RxCK7 RxSYNC7 DSTo7 TxCK7 TxSYNC7 PLLREF0 PLLREF1 REFCK0 IMA PRI SEC F0o C2o C4o PLL ATM BUS F0 C2 ST-BUS Timing F0 = FPi = TxSYNCo F0 = RxBF = RxSYNCo C4 = RxDLC = RxCKo C4 = CKi = TxCKo Bits C4 6 6 6 6 6 6 RPOS RNEG E2i TPOS TNEG T2o DSTo RxDLC RxBF DSTi CKi FPi Framer 8/8 |
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