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MT9072AB Datasheet(PDF) 249 Page - Zarlink Semiconductor Inc

Part # MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 249 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
249
Zarlink Semiconductor Inc.
Figure 37 - ST-BUS 8.192 Mb/s Functional Timing Diagram for CSTo/CSTi CAS
Figure 38 - ST-BUS 8.192 Mb/s Functional Timing Diagram for CSTo/CSTi CCS
19.2
T1 Mode
AC Electrical Characteristics - IMA BackplaneTiming
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
C1.5i Clock Width High or Low
tC1.5W
295
324
353
ns
2
Frame Pulse Setup
tFPS
50
ns
3
Frame Pulse Hold
tFPH
50
ns
4
Serial Input Setup
tSIS
30
ns
5
Serial Input Hold
tSIH
50
ns
6
Clock output delay
tcod
50
ns
7
Serial Output Delay
tSOD
20
90
125
ns
150 pF load on CSTo and
DSTo
Timeslot 127
Bit 0
Channel
0
Channel
1
Channel
2
ST-BUS Bit Cells
8Mb/s
FPi
(ST-BUS F16i)
Channel
3
Chan 0
Data
Chan 1
Data
Chan 2
Data
Chan 0
Data
Chan 1
Data
Chan 2
Data
CSTi0
CSTo0
Note: In Cas only the lower nibble of the stream is used
Note: The ABCD bits are bit 3 to bit 0 respectively
Timeslot 127
Bit 0
Channel
0
Channel
1
Channel
2
ST-BUS Bit Cells
8Mb/s
FPi
(ST-BUS F16i)
Channel
3
Note: In CCS the complete Byte is used in accordance with CCS Map register Y07. Any 3 CSTi/CSTo channels are
CSTo0
CSTo0
CCS
Chan 0
CCS
Chan 1
CCS
Chan 0
CCS
Chan1
used



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