CLC2011ISO8X datasheet(11/17 Pages) EXAR

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exar.com/CLC2011

Rev 1D

CLC2011, CLC4011

Table 1 provides the recommended RS for various capacitive

loads. The recommended RS values result in approximately

<1dB peaking in the frequency response. The Frequency

Response vs. CL plot, on page 6, illustrates the response

of the CLCx011.

CL (pF)

RS (Ω)

-3dB BW (MHz)

10pF

2.2

20pF

2.4

50pF

2.5

100pF

100

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of

additional overshoot and ringing.

Overdrive Recovery

An overdrive condition is defined as the point when either

one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for the

amplifier to return to its normal or linear operating point. The

recovery time varies, based on whether the input or output

is overdriven and by how much the range is exceeded.

The CLCx011 will typically recover in less than 50ns from

an overdrive condition. Figure 8 shows the CLC2011 in an

overdriven condition.

Figure 8: Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. Exar has evaluation boards to

use as a guide for high frequency layout and as an aid in

device testing and characterization. Follow the steps below

as a basis for high frequency layout:

■

Include 6.8µF and 0.1µF ceramic capacitors for power supply

decoupling

■

Place the 6.8µF capacitor within 0.75 inches of the power pin

■

Place the 0.1µF capacitor within 0.1 inches of the power pin

■

Remove the ground plane under and around the part,

especially near the input and output pins to reduce parasitic

capacitance

■

Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more

information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB006

CLC2011 in SOIC

CEB010

CLC2011 in MSOP

CEB019

CLC4011 in TSSOP

CEB018

CLC4011 in SOIC

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 9-16 These evaluation boards are built for dual-

supply operation. Follow these steps to use the board in a

single-supply application:

1. Short -VS to ground.

2. Use C3 and C4, if the -VS pin of the amplifier is not

directly connected to the ground plane.

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