BD9470AFM・BD9470AEFV

○Explanation of OVP holding function in narrow PWM duty

DCDC operates only in the duration of PWM=High while narrow PWM is inputted, output voltage drops when PWM=0%.

But, DCDC is operated by coping voltage even if PWM=Low duration in this IC and output voltage will not drops.

①PWM=High, normal operation.

②OVP voltage is copied into IC when PWM is from High to Low.OVP voltage will be copied under 1BIT at this time. For

example: if OVP=2.43V, the copied voltage is 2.4V in IC.

③VOUT is discharged by OVP resistance.

④When copied OVP_COPY＞OVP pin voltage, DCDC is operated, when OVP_COPY＜OVP voltage, DCDC is stops.

When operates in PWM=0%, the point④ will be repeated and repeated, so the output voltage will not drops naturally.

○Condition of copy OVP voltage

The copied OVP pin voltage as above explanation, it has upper and lower 1BIT difference according to below condition.

Conditions of copy upper 1BIT

：From startup to completion of step-up

：OVP detection state

Conditions of copy lower 1BIT

：Normal operation state ( OVP undetected state)

※The reason about why copy the voltage of upper 1BIT when OVP is detected

When OVP is detected by OVP=3V and stops DCDC operation. After that while PWM=Low and if copy lower 1BIT voltage will results in

OVP=2.9V and release OVP detection function, therefore it is designed to copy upper 1BIT when OVP is detected.

Figure 25. Timing chart 2 of KEEP_OVP

PWM

OVP COPY

OVP

N

①

②

④

③

20/35

TSZ02201-0F10C1002000-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

19.Oct.2013 Rev.003

www.rohm.com

TSZ22111・15・001