FDC37N869 datasheet(21/147 Pages) SMSC

21 / 147 page

SMSC DS – FDC37N869

Page 21

Rev. 11/09/2000

STATUS REGISTER B (SRB)

Status Register B (Base Address + 1) is read-only and monitors the state of several disk interface pins in PS/2

interface mode (Table 7) and Model 30 interface mode (Table 8). SRB can be accessed at any time when in these

modes. During a read in PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state.

PS/2 Interface Mode

Table 7 - SRB PS/2 Mode

DRIVE

SEL0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT EN1 MOT EN0

RESET

CONDITION

Motor Enable 0, Bit 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a

software reset.

Motor Enable 1, Bit 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a

software reset.

Write Gate, Bit 2

Active high status of the WGATE disk interface output.

Read Data Toggle, Bit 3

Every inactive edge of the RDATA input causes this bit to change state.

Write Data Toggle, Bit 4

Every inactive edge of the WDATA input causes this bit to change state.

Drive Select 0, Bit 5

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware

reset, it is unaffected by a software reset.

Reserved, Bits 6 - 7

Always read as a logic “1”.

FDC37N869 Datasheet(PDF) 21 Page - SMSC Corporation