S25FS064S datasheet(21/147 Pages) CYPRESS

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Document Number: 002-03631 Rev. *C

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S25FS064S

PRELIMINARY

there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When

there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency.

The next interface state following the last latency cycle is a DDR Single, or Quad Output Cycle, depending on the instruction.

4.3.20 DDR Quad Output Cycle — Memory to Host Transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the rising edge of SCK

and four bits on the falling edge in each cycle. The host keeps CS# low.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.

4.4

Configuration Register Effects on the Interface

The configuration register 2 volatile bits 3 to 0 (CR2V[3:0]) select the variable latency for all array read commands except Read,

RUID and Read SDFP (RSFDP). Read always has zero latency cycles. RSFDP always has 8 latency cycles. The variable latency is

also used in the OTPR, ECCRD, and RDAR commands.

The configuration register bit1 (CR1V[1]) selects whether Quad mode is enabled to switch WP# to IO2 function, RESET# to IO3

function, and thus allow Quad I/O Read and QPI mode commands. Quad mode must also be selected to allow DDR Quad I/O Read

commands.

4.5

Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These

are described below. Other software managed protection methods are discussed in the software section of this document.

4.5.1

Power-Up

When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue

to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface

Standby state.

4.5.2

Low Power

When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

4.5.3

Clock Pulse Count

The device verifies that all non-volatile memory and register data modifying commands consist of a clock pulse count that is a

multiple of eight bit transfers (byte boundary) before executing them. A command not ending on an 8 bit (byte) boundary is ignored

and no error status is set for the command.

4.5.4

Deep Power Down (DPD)

In DPD mode the device responds only to the Resume from DPD command (RES ABh). All other commands are ignored during

DPD mode, thereby protecting the memory from program and erase operations. If the IO3_RESET# function has been enabled

(CR2V[5]=1) or if RESET# is active, IO3_RESET# or RESET# going low will start a hardware reset and release the device from

DPD mode.

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