Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

GL811USB Datasheet(PDF) 23 Page - List of Unclassifed Manufacturers

Part # GL811USB
Description  USB 2.0 to ATA / ATAPI Bridge Controller
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC - List of Unclassifed Manufacturers

GL811USB Datasheet(HTML) 23 Page - List of Unclassifed Manufacturers

Back Button GL811USB Datasheet HTML 19Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 20Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 21Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 22Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 23Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 24Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 25Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 26Page - List of Unclassifed Manufacturers GL811USB Datasheet HTML 27Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 36 page
background image
GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
©2000-2002 Genesys Logic Inc.—All rights reserved.
Page 22
6.4.3 Ultra DMA data transfer
6.4.3.1 Ultra DMA data burst timing requirements
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
Mode 4
(in ns)
Name
min
max
min
max
min
max
min
max
Min
max
Comment
t2CYCTYP
240
160
120
90
60
Typical sustained average two
cycle time
tCYC
112
73
54
39
25
Cycle time allowing for
asymmetry and clock variations
t2CYC
230
154
115
86
57
Two cycle time allowing for clock
variations
tDS
15
10
7
7
5
Data setup time at recipient
tDH
5
5
5
5
5
Data hold time at recipient
tDVS
70
48
30
20
6
Data valid setup time at sender
tDVH
6
6
6
6
6
Data valid hold time at sender
tFS
0
230
0
200
0
170
0
130
0
120
First STORBE time
tLI
0
150
0
150
0
150
0
100
0
100
Limited interlock time
tMLI
20
20
20
20
20
Interlock time with minimum
tUI
0
0
0
0
0
Unlimited interlock time
tAZ
10
10
10
10
10
Maximum time allowed for
output drivers to release
tZAH
20
20
20
20
20
Minimum delay time required for
output
tZAD
0
0
0
0
0
Drivers to assert or negate
tENV
20
70
20
70
20
70
20
55
20
55
Envelope time
tSR
50
30
20
NA
NA
STROBE to DMARDY_ time
tRFS
75
70
60
60
60
Ready to final STROBE time
tRP
160
125
100
100
100
Minimum time to assert STOP or
negate DMARQ
tIORDYZ
20
20
20
20
20
Maximum time before releasing
IORDY
tZIORDY
0
0
0
0
0
Minimum time before driving
STROBE
tACK
20
20
20
20
20
Setup and hold times for
DMACK_
tSS
50
50
50
50
50
Time from STROBE edge to
negation of DMARQ or assertion
of STOP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com