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MCP73830 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP73830 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 22 page ![]() 2011-2014 Microchip Technology Inc. DS20005049D-page 3 MCP73830/L 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD...................................................................................7.0V All Inputs and Outputs w.r.t. VSS ............... -0.3 to (VDD+0.3)V Maximum Junction Temperature, TJ ............ Internally Limited Storage temperature .....................................-65°C to +150°C ESD protection on all pins Human Body Model (1.5 kW in Series with 100 pF) 2kV Machine Model (200 pF, No Series Resistance) .............300V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all limits apply for VDD= [VREG(Typical) + 0.3V] to 6V, TA = -40°C to +85°C. Typical values are at +25°C, VDD = [VREG (Typical) + 1.0V] Parameters Sym. Min. Typ. Max. Units Conditions Supply Input Input Voltage Range VDD 3.75 — 6 V Supply Current ISS — 0.6 2 µA Shutdown; VDD VSTOP - 300 mV — 500 900 µA Charging — 25 50 µA Standby; CE = VDD Battery Discharge Current Output Reverse Leakage Current IDISCHARGE 10 15 µA Charge Complete; VDD is Present — 0.5 — µA Shutdown (VDD VBAT, or VDD < VSTOP) — 0.5 — µA Standby; CE = VDD Undervoltage Lockout UVLO Start Threshold VSTART 3.45 3.6 3.75 V VDD Low-to-High UVLO Stop Threshold VSTOP 3.15 3.3 3.45 V VDD High-to-Low UVLO Hysteresis VHYS — 300 — mV Voltage Regulation (Constant Voltage Mode) Regulated Output Voltage Options VREG —4.20 — V VDD = [VREG(Typical)+1V] IOUT = 30 mA Output Voltage Tolerance VRTOL -0.75 — 0.75 % TA= -5°C to +55°C Line Regulation V BAT/VBAT)/ V DD| — 0.2 0.3 %/V VDD = [VREG(Typical)+1V] to 12V IOUT = 30 mA Load Regulation V BAT/VBAT|— 0.2 0.3 % IOUT = 30 mA - 150 mA VDD = [VREG(Typical)+1V] Supply Ripple Attenuation PSRR 52 — dB IOUT = 30 mA, 10 Hz to 1 kHz 47 — dB IOUT = 30 mA, 10 Hz to 10 kHz Note 1: Not production tested. Ensured by design. |
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