2

CDP68HC68P1

Pin Descriptions

The 4 possible combinations of these pins allow 4 I/Os to

share a common chip enable. When the levels at these pins

match those of the identify bits in the control word, the serial

bus is enabled. The chip identify pins will retain their

previous logic state if the lines driving them become Hi-Z.

MISO - Master-in, Slave out pin. Data bytes are shifted out

at this pin most significant bit first. When the chip enable

signal is high, this pin is Hi-Z.

MOSI - Master-out, Slave in pin. Data bytes are shifted in at

this pin most significant bit first. This pin will retain its

previous logic state if its driving line becomes Hi-Z.

SCK - Serial clock input. This input causes serial data to be

latched from the MOSI input and shifted out on the MISO

output.

CE - A negative chip enable input. A high to low transition on

this pin latches the inactive SCK polarity and compare flag

and indicates the start of a data transfer. The serial interface

logic is enabled only when CE is low. This pin will retain its

previous logic state if its driving line becomes Hi-Z.

D0 -D7 - I/O Port pins. Individual programmable inputs or

outputs.

All pins except the power supply lines and MISO have

Schmitt-trigger buffered inputs.

FIGURE 1. SINGLE PORT I/O BLOCK DIAGRAM

SHIFT REGISTER

CONTROL

LOGIC

COMPARATOR

INPUT/OUTPUT

D0 - D7

DIRECTION

REGISTER

DIRECTION

REGISTER

CE

SCK

MOSI

MISO

FIGURE 2. SINGLE PORT I/O

CHIP

DATA OUT

CLOCK

CE

CHIP

IDENTIFY

I/O PORT

DATA IN

DATA

IN/OUT

D0 - D7

CDP68HC68P1

SCK

MISO

MOSI

ENABLE