74LVC4066 datasheet(2/23 Pages) PHILIPS

2 / 23 page

2003 Aug 12

Philips Semiconductors

Product speciﬁcation

Quad bilateral switches

74LVC4066

FEATURES

• Very low ON resistance:

– 7.5

Ω (typical) at VCC = 2.7 V

– 6.5

Ω (typical) at VCC = 3.3 V

–6

Ω (typical) at VCC =5V.

• ESD protection:

– HBM EIA/JESD22-A114-A Exceeds 2000 V

– MM EIA/JESD22-A115-A Exceeds 200 V.

• High noise immunity

• CMOS low power consumption

• Latch up performance exceeds 250 mA

• Complies with JEDEC standard no. 8-1A

• Direct interface TTL-levels.

DESCRIPTION

The 74LVC4066 is a high-speed Si-gate CMOS device.

The 74LVC4066 has four independent analog switches.

Each switch has two input/output terminals (nY and nZ)

and an active HIGH enable input (nE). When nE is LOW,

the analog switch is turned off.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N + ((CL +CS) × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

CS = switch capacitance.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPZH/tPZL

turn-on time E to Vos

CL = 50 pF; RL = 500 Ω; VCC = 3 V

2.5

CL = 50 pF; RL = 500 Ω; VCC = 5 V

1.9

tPHZ/tPLZ

turn-off time E to Vos

CL = 50 pF; RL = 500 Ω; VCC = 3 V

3.4

CL = 50 pF; RL = 500 Ω; VCC = 5 V

2.5

input capacitance

VCC = 3 V

3.5

CPD

power dissipation capacitance

VCC = 3.3 V; notes 1 and 2

12.5

switch capacitance

OFF-state

8.0

ON-state

14.0

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