PM8313 datasheet(49/192 Pages) PMC

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PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

When enabled, the XFDL continuously transmits the flag character (01111110).

Data bytes to be transmitted are written into the Transmit Data Register. After the

parallel-to-serial conversion of each data byte, an interrupt is generated to signal

the controller to write the next byte into the Transmit Data Register. After the last

data frame byte, the CRC word (if CRC insertion has been enabled), or a flag (if

CRC insertion has not been enabled) is transmitted. The XFDL then returns to

the transmission of flag characters. The last data frame byte can be indicated by

either writing to the EOM bit in the XFDL configuration register or by setting the

TDLEOMI input high.

If there are more than five consecutive ones in the raw transmit data or in the

CRC data, a zero is stuffed into the serial data output. This prevents the

unintentional transmission of flag or abort characters.

Abort characters can be continuously transmitted at any time by setting a control

bit. During transmission, an underrun situation can occur if data is not written to

the Transmit Data Register before the previous byte has been depleted. In this

case, an abort sequence is transmitted, and the controlling processor is notified

via the UDR status bit.

8.7

Alarm And Control Channel Bit Oriented Code Transmitter

The XBOC Bit-Oriented Code Transmitter TSB transmits 63 of the possible 64

bit-oriented codes (BOCs) over the DS3 C-bit parity far end alarm and control

(FEAC) channel. The 64th possible code (111111) is similar to the HDLC idle

sequence and is used in the XBOC to disable transmission of any bit-oriented

codes.

BOCs are transmitted on the FEAC as a 16 bit sequence consisting of 8 ones, 1

zero, 6 code bits, and 1 trailing zero (111111110xxxxxx0). An internal register is

loaded with the 6 code bits to be transmitted. The 16 bit sequence is

continuously transmitted until disabled by forcing the six code bits to 111111.

8.8

M23 Multiplexer

The MX23 M23 Multiplexer integrates circuitry required to asynchronously

multiplex and demultiplex seven DS2 streams into, and out of, an M23 or C-bit

Parity formatted DS3 serial stream.

When multiplexing seven DS2 streams into an M23 formatted DS3 stream, the

MX23 TSB performs rate adaptation to the DS3 by integral FIFO buffers,

controlled by timing circuitry. The FIFO buffers accommodate in excess of 5.0

UIpp of sinusoidal jitter on TD2CLK for all jitter frequencies. The C-bits are also

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