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DS000002251A-page 27

USB2507

5.6

Reset

There are two different resets that the Hub experiences. One is a hardware reset (via the RESET_N pin) and the second

is a USB Bus Reset.

5.6.1

EXTERNAL HARDWARE RESET_N

A valid hardware reset is defined as, assertion of RESET_N for a minimum of 1us after all power supplies are within

operating range. While reset is asserted, the Hub (and its associated external circuitry) consumes less than 500

A of

current from the upstream USB power source (300

A for the Hub and 200A for the external circuitry).

Assertion of RESET_N (external pin) causes the following:

1.

All downstream ports are disabled, and PRTPWR power to downstream devices is removed.

2.

The PHYs are disabled, and the differential pairs will be in a high-impedance state.

3.

All transactions immediately terminate; no states are saved.

4.

All internal registers return to the default state (in most cases, 00(h)).

5.

The external crystal oscillator is halted.

6.

The PLL is halted.

7.

LED indicators are disabled.

The Hub is “operational” 500

s after RESET_N is negated.

Once operational, the Hub immediately reads OEM-specific data from the external EEPROM (if the SMBus option is not

disabled).

5.6.1.1

RESET_N for Strapping Option Configuration

FIGURE 5-2:

RESET_N TIMING FOR DEFAULT/STRAP OPTION MODE

TABLE 5-5:

RESET_N TIMING FOR DEFAULT/STRAP OPTION MODE

Name

Description

MIN

TYP

MAX

Units

t1

RESET_N Asserted.

1

sec

t2

Strap Setup Time

16.7

nsec

t3

Strap Hold Time.

16.7

1400

nsec

t4

hub outputs driven to inactive logic states

2.0

1.5

sec

t1

t4

t5

t6

t7

t8

Valid

Don’t Care

Don’t Care

Driven by Hub if strap is an output.

RESET_N

VSS

Strap Pins

VSS

Hardware

reset

asserted

Read Strap

Options

Drive Strap

Outputs to

inactive

levels

Attach

USB

Upstream

USB Reset

recovery

Idle

Start

completion

request

response

t2

t3