BLUENRG-134 datasheet(21/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

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

ADC



MFT1



MFT2



RTC



WDG

By default all peripherals APB clock are enabled.

The following clocks are enabled/disabled automatically:



Processor clock (disabled in sleep mode)



RAM clock (disabled if processor clock, SPI clock and BLE clock are all disabled)

3.5.1

Reset management

Figure 6: "Reset and wakeup generation" shows the general principle of reset. Releasing

the Reset pin puts the chip out of shutdown state. The wakeup logic is powered and

receives the POR. Each time the wake-up controller decides to exit sleep or standby

modes, it will generate a reset for the core logic. The core logic can also be reset by:



Watchdog



Reset request from the processor (system reset)



LOCKUP state of the Cortex-M0.

The SWD logic is reset by the POR. It is important to highlight that reset pin actually power

down chip, so it is not possible to perform debug access with system under reset.

Figure 6: Reset and wakeup generation

3.5.1.1

Power-on-Reset

The Power-on-Reset (POR) signal is the combination of the POR signal and the BOR

signal generated by the analog circuitry contained in the BlueNRG-1 device. The

combination of these signals is used to generate the input to the Cortex-M0 which is used

to reset the debug access port (DAP) of the processor. It is also used to generate the

signal which resets the debug logic of the Cortex-M0. The POR signal also resets the TAP

controller of the BlueNRG-1 and a part of the flash controller (managing the Flash memory

boot, which does not need to be impacted by system resets).

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