USB3250 datasheet(24/46 Pages) MICROCHIP

24 / 46 page

USB3250

DS00002142A-page 24

 2013 - 2016 Microchip Technology Inc.

The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state deasserts RXAC-

TIVE and RXVALID. When the RESET signal is deasserted the Receive State Machine enters the RX Wait state and

starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected the state machine will enter the Strip

SYNC state and assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits

long or as short as 12 bits long when at the end of five hubs. As a result, the state machine may remain in the Strip

SYNC state for several byte times before capturing the first byte of data and entering the RX Data state.

After valid serial data is received, the state machine enters the RX Data state, where the data is loaded into the RX

Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must clock the data off the RXDATA

bus on the next rising edge of CLKOUT. If OPMODE = Normal, then stuffed bits are stripped from the data stream. Each

time 8 stuffed bits are accumulated the state machine will enter the RX Data Wait state, negating RXVALID thus skipping

a byte time.

When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE and RXVALID. After

the EOP has been stripped the Receive State Machine will reenter the RX Wait state and begin looking for the next

packet.

The behavior of the Receive State Machine is described below:

• RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.

• In the RX Wait state the receiver is always looking for SYNC.

• The USB3250asserts RXACTIVE when SYNC is detected (Strip SYNC state).

• The USB3250 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty (Strip EOP state).

• When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.

• RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur

if 8 stuffed bits have been accumulated.

• The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state).

• Figure 7-10 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR

and RXDATA signals.

Note 7-1

The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for

decoding.

Note 7-2

Figure 7-10, Figure 7-11 and Figure 7-12 are timing examples of a HS/FS Macrocell when it is in HS

mode. When a HS/FS Macrocell is in FS Mode (8-bit mode) there are approximately 40 CLK60 cycles

every byte time. The Receive State Machine assumes that the SIE captures the data on the RXDATA

bus if RXACTIVE and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one

CLK60 per byte time.

FIGURE 7-9:

RECEIVE TIMING FOR 16-BIT DATA, ODD BYTE COUNT

PID

DATA

DAT

CRC

EOP

PID

DATA (0)

DATA (1)

DATA (2)

DATA (3)

CRC (LO)

CRC (HI)

123

SYNC

CLK30

DATA[7:0]

RXACTIVE

RXVALID

DP/DM

DATA[15:8]

VALIDH

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