LAN8700 datasheet(21/74 Pages) MICROCHIP

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DS00002260A-page 21

LAN8700/LAN8700i

ticity buffering. The elasticity buffer does not affect the Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater.

To tolerate the clock variations specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum of ±10

bits.

4.6.2.2

CRS_DV - Carrier Sense/Receive Data Valid

The CRS_DV is asserted by the LAN8700/LAN8700i when the receive medium is non-idle. CRS_DV is asserted asyn-

chronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when

squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected, carrier is said to be

detected.

Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first

di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble boundaries). If the LAN8700/LAN8700i has

additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the LAN8700/LAN8700i

shall assert CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on

cycles of REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries CRS_DV toggles

at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before RX_DV (i.e. the FIFO still has bits

to transfer when the carrier event ends.) Therefore, the MAC can accurately recover RX_DV and CRS.

During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is

considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to

REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place.

4.6.3

MII VS. RMII CONFIGURATION

The LAN8700/LAN8700i must be configured to support the MII or RMII bus for connectivity to the MAC. This configu-

ration is done through the COL/RMII/CRS_DV pin. To select MII mode, float the COL/RMII/CRS_DV pin. To select RMII

mode, pull the pin high with an external resistor (see Table 4-3, “Boot Strapping Configuration Resistors,” on page 25)

to VDDIO. On the rising edge of the internal reset (nreset), the register bit 18.14 (MIIMODE) is loaded based on the

strapping of the COL/RMII/CRS_DV pin.

Most of the MII and RMII pins are multiplexed. Table 4-2, "MII/RMII Signal Mapping", shown below, describes the rela-

tionship of the related device pins to what pins are used in MII and RMII mode.

TABLE 4-2:

MII/RMII SIGNAL MAPPING

Signal Name

MII Mode

RMII Mode

TXD0

TXD1

TX_EN

RX_ER/

RXD4

RX_ER/

RXD4/

RX_ER

Note 4-2

COL/RMII/

CRS_DV

COL

CRS_DV

RXD0

RXD1

TXD2

Note 4-1

TXD3

Note 4-1

TX_ER/

TXD4

TX_ER/

TXD4

CRS

RX_DV

RXD2

RXD3/

nINTSEL

RXD3

TX_CLK

RX_CLK

CLKIN/

XTAL1

CLKIN/

XTAL1

REF_CLK

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