UT8Q1024K8 datasheet(2/15 Pages) AEROFLEX

2 / 15 page

PIN NAMES

Notes:

1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low

simultaneously while G is low.

DEVICE OPERATION

Each die in the UT8Q1024K8 has three control inputs called

Enable (En), Write Enable (Wn), and Output Enable (G); 19

address inputs, A(18:0); and eight bidirectional data lines,

DQ(7:0). The device enable (En) controls device selection,

active, and standby modes. Asserting En enables the device,

causes I

DD to rise to its active value, and decodes the 19 address

inputs to each memory die . Wn controls read and write

operations. During a read cycle, G must be asserted to enable

the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than VIH (min) withEn and G less

than VIL (max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or valid

address to valid data output.

SRAM Read Cycle 1, the Address Access is initiated by a change

in address inputs while the chip is enabled with G asserted and

Wn deasserted. Valid data appears on data outputs DQ(7:0) after

the specified t

AVQV is satisfied. Outputs remain active

throughout the entire cycle. As long as device enable and output

enable are active, the address inputs may change at a rate equal

to the minimum read cycle time (tAVAV).

SRAM Read Cycle 2, the Chip Enable-controlled Access is

initiated by En going active while G remains asserted, Wn

remains deasserted, and the addresses remain stable for the

entire cycle. After the specified t

ETQV is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data

outputs DQ(7:0).

SRAM Read Cycle 3, the Output Enable-controlled Access is

initiated by G going active while En is asserted, Wn is

deasserted, and the addresses are stable. Read access time is

tGLQV unless tAVQV or tETQV have not been satisfied.

A(18:0)

Address

DQ(7:0)

Data Input/Output

Device Enable

WriteEnable

Output Enable

VDD

Power

VSS

Ground

Figure 2. 25ns SRAM Pinout (44)

A18

A17

A16

A15

DQ7

DQ6

VSS

VDD

DQ5

DQ4

A14

A13

A12

A11

A10

DQ0

DQ1

VDD

VSS

DQ2

DQ3

I/O Mode

Mode

3-state

Standby

Data in

Write

3-state

Read

Data out

Read

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