MLX71122_16 datasheet(44/59 Pages) MELEXIS

44 / 59 page

MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 44 of 59

390 10 71122 01

MFO

[11:8]

multi functional output

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Z state

SPI read-out

MFO = 0

MFO = 1

analog RO output

analog IFF output

resistor (for test purposes)

lock detect output

N divider output (for test purposes)

R divider output (for test purposes)

CCO output (for test purposes)

prescaler MC bit output with SCLK as clock (for test)

N divider output with SCLK as clock (for test)

R divider output with SCLK as clock (for test)

RIFF output with SCLK as clock (for test)

#default

4.1.5. Control Word R4

Name

Bits

Description

[10:0]

reference divider range

000 0100 1011

value is 75

#default

R counter range: 3 to 2047

AGCMODE

[11]

AGC delay mode

gain decrease and increase with delay

gain decrease without delay, gain increase with delay

#default

selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3)

4.1.6. Control Word R5

Name

Bits

Description

RIFF

[10:0]

reference divider value for IFF adjustment

010 1010 1100

value is 684

#default

IFF counter range: 4 to 2047

MODSEL

[11]

demodulation selection

FSK demodulation

ASK demodulation

#default

selects modulation type when chip is controlled via SPI mode

MLX71122 Datasheet(PDF) 44 Page - Melexis Microelectronic Systems

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