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LPC47B272 Datasheet(PDF) 13 Page - SMSC Corporation |
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LPC47B272 Datasheet(HTML) 13 Page - SMSC Corporation |
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13 / 195 page  SMSC LPC47B27x - 13 - Rev. 04-17-07 DATASHEET BLOCK DIAGRAM FIGURE 1 – LPC47B27x BLOCK DIAGRAM REFERENCE DOCUMENTS 1. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X 2. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. 3. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. 4. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 5. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. 6. SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts. 7. SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC Floppy Disk Controllers. 3 VOLT OPERATION / 5 VOLT TOLERANCE The LPC47B27x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: • LAD[3:0] • nLFRAME • nLDRQ • nLPCPD The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins: • nPCI_RESET • PCI_CLK • SER_IRQ • nIO_PME nDSR1, nDCD1, nRI1, nDTR1 TXD1, nCTS1, nRTS1 nINIT , nALF LPC BUS INTERFACE MULTI-MODE PARALLEL PORT/FDC MUX 16C550 COMPATIBLE SERIAL PORT 1 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED ADDRESS BUS DATA BUS CLOCK GEN CLOCKI 14MHz nINDEX nTRK0 nDSKCHG nWRPRT nWGATE DENSEL nDIR nSTEP nHDSEL nDS0 nMTR0 RDATA RCLOCK WDATA WCLOCK nWDATA nRDATA TXD2(IRTX), nCTS2, nRTS2* RXD2(IRRX)* nDSR2, nDCD2, nRI2, nDTR2* RXD1 PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE DIGITAL DATA SEPARATOR WITH WRITE PRECOM- PENSATION IRRX, IRTX DRVDEN0 DRVDEN1* SERIAL IRQ SER_IRQ PCI_CLK 8042 KCLK KDATA MCLK MDATA GATEA20, KRESET PME Vcc Vss nIO_PME WDT * Denotes Multifunction Pins CLK32 32KHz VTR SMI LPC Bus Signals CONFIGURATION REGISTERS CONTROL BUS Fan Control FAN1* FAN2* FAN_TACH1* FAN_TACH2* GENERAL PURPOSE I/O GP1[0:7]* GP2[0:2,4:7]* MPU-401 SERIAL PORT MIDI_IN MIDI_OUT Game Port ... Game Port Signals* (1-Dual) GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]* ACPI BLOCK nIO_SMI |
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