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PI6C103L Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation |
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PI6C103L Datasheet(HTML) 2 Page - Pericom Semiconductor Corporation |
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2 / 12 page ![]() 223 PS8315-2 04/08/99 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C103 Precision Clock Synthesizer for Mobile PCs Pin Description Notes: 1. VDD and VSS names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the same voltage VDD pins tied to a common supply and all VSS pins being common. The VDD/VSS naming convention above is done to show how the pinout is dominated by the need to isolate all the signals. 2. The output frequency at this pin is dependent on the power on strapping option at pin 27. A 48 MHz output when power-on strapped LOW, and 24 MHz output when strapped HIGH. This pin also serves as Hi-Z state strapping option during power-on configuration. During power-on, the PI6C103 will sample the value at this pin. Strapped LOW for Hi-Z state mode and HIGH for normal operation. 3. This is a dual function pin. During power-on, all clock outputs are disabled, and the PI6C103 will sample the spread spectrum enable/disable strapping option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 MHz reference clock output. The Power-on latency needs to be less than 3ms after the supply voltage stabilized. 4. This is a dual function pin. During power-on, all clocks are disabled, and PI6C103 will sample the SEL48# strapping option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 MHz reference clock output. The power- on latency needs to be less than 3ms after the supply voltage stabilized. 5. Internally pulled up with resistor min.value of 50kΩ. e g a k c a P n i P - 8 2 e p y Tl o b m y Sn o it p i r c s e D n i P. y t Q 21 t u p n IN I _ L A T Xt u p n i l a t s y r c z H M 8 1 3 . 4 1 31 t u p t u OT U O _ L A T Xz H M 8 1 3 . 4 1t u p t u o l a t s y r c 41 t u p t u OF _ K L C I C Pt u p t u o k c o l c I C P g n i n n u r e e rf V 3 . 3 1 1 , 0 1 , 9 , 6 , 55 t u p t u O] 5 - 1 [ K L C I C Pst u p t u o k c o l C I C P V 3 . 3 3 11 t u p t u Oz H M 8 4t u p t u o k c o l c z H M 8 4 V 3 . 3 4 11 t u p t u O# S T / z H M 4 2 - 8 4 d n a t u p t u o z H M 4 2 r o 8 4 V 3 . 3Z -i Hn o it p o g n i p p a rt s e t a t s ) 5 , 2 ( r e t n E = w o L p a rt SZ -i Hn o it a r e p o l a m r o N = h g i H p a rt S , g n it s e t r o f e d o m e t a t s 6 11 t u p n I# 6 6 / 0 0 1 L E S k c o l c U P C z H M 6 6 r o z H M 0 0 1 g n il b a n e r o f t c el e S ) 5 ( z H M 6 6 = L ,z H M 0 0 1 = H 7 11 t u p n I# N W D _ R W P5 W O L n e h w e d o m n w o d r e w o p s r e t n e e ci v e D 8 11 t u p n I# P O T S _ U P Ce t a t s W O L n i s k c o l c U P C p o t s , w o L n e h W 0 21 t u p n I# P O T S _ I C P t u p t u o F _ K L C I C P r o f t p e c x e e t a t s W O L n i s k c o l c I C P ll a s p o t s , W O L l a n g i s n e h W ) 5 ( 4 2 , 3 22 t u p t u O] 0 - 1 [ K L C U P Cst u p t u o k c o l c U P C V 5 . 2 6 21 t u p t u O# d a e r p S / 0 F E R m u rt c e p s d a e r p s n o - r e w o p d n a t u p t u o k c o l c e c n e r e f e r z H M 8 1 3 . 4 1 V 3 . 3 n o it p o p a rt s el b a n e 5 , 3 () el b a n e g n i k c o l c m u rt c e p s d a e r p S = w o L p a rt S el b a si d g n i k c o l c m u rt c e p s d a e r p S = h g i H p a rt S 7 21 t u p t u O# 8 4 L E S / 1 F E R z H M 4 2 / 8 4 n o - r e w o p d n a t u p t u o k c o l c e c n e r e f e r z H M 8 1 3 . 4 1 V 3 . 3 5 , 4 n o it p o p a rt s t c el e s W O L d e p a rt s n e h w z H M 8 4 = t u p t u o 4 1 n i P H G I H d e p p a rt s n e h w z H M 4 2 = t u p t u o 4 1 n i P 8 2 , 9 1 , 2 1 , 81 r e w o PV D D r e w o P V 3 . 3 1 2 , 5 1 , 7 , 1r e w o PV S S d n u o r G V 3 . 3 5 21 r e w o PV 2 D D r e w o P V 5 . 2 2 21 r e w o PV 2 S S d n u o r G V 5 . 2 |
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