SST49LF160C datasheet(13/37 Pages) MICROCHIP

13 / 37 page

DS20005099B

02/16

16 Mbit LPC Flash

SST49LF160C

EOL Data Sheet

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be

terminated. The host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to return the interface to

ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence,

such as the Erase or Program commands, ABORT doesn’t interrupt the entire command sequence,

only the current bus cycle of the command sequence. The host can re-send the bus cycle for the

aborted command and continue the command sequence after the device is ready again.

Response to Invalid Fields for LPC Memory Cycle

During an on-going LPC bus cycle, the SST49LF160C will not explicitly indicate that it has received

invalid field sequences. The response to specific invalid fields or sequences is described as follows:

ID mismatch:

ID information is included in the address bits of every LPC Memory cycle. Address bits [A25:A23, A21]

are used to select the device with proper IDs. The SST49LF160C will compare the ID bits in the

address field with ID[3:0]. If the ID bits in the address do not correspond to the hardware ID pins the

device will ignore the cycle. See Device Commands section for details.

Address out of range:

The address sequence is 8 fields long (32 bits). The address bits [A25:A23, A21] for the SST49LF160C

are used to select the device with proper IDs. Unused most significant address bits must be set to “1”

during LPC protocol transfer. Address A22 has the special function of directing Read and Write opera-

tions to the flash core (A22=1) or to the register space (A22=0).

For the Boot Device (ID[3:0]=0000b), the SST49LF160C decodes the physical addresses of the Top

128 KByte Blocks (including Boot Block) at both system memory ranges indicated in Table 6.

Once valid START, CYCTYPE + DIR, and address range (including ID bits) are received, the

SST49LF160C will always complete the bus cycle. However, if the device is busy performing a flash

Erase or Program operation, no new internal memory Write will be executed. As long as the states of

LAD[3:0] and LFRAME# are known, the response of the SST49LF160C to signals received during the

LPC cycle is predictable.

Table 6: Boot Device Physical Addresses Decoding

Memory Range

Also mapped at Memory Range

FFFF FFFFH - FFFE 0000H

000F FFFFH - 000E 0000H

SST49LF160C Datasheet(PDF) 13 Page - Microchip Technology