MGC3030 datasheet(34/50 Pages) MICROCHIP

34 / 50 page

MGC3030/3130

DS40001667D-page 34

Advance Information

 2012-2015 Microchip Technology Inc.

6.0

APPLICATION ARCHITECTURE

The standard MGC3X30 implementation is a single-

zone design. This configuration is based on one

MGC3X30 connected to an application host via I2C™

with MGC3X30 being Slave and Application Host being

Master. A total of three lines are needed for the I2C

interface (see Figure 6-1).

Data reporting and flow-control scenarios are

described below for I2C communication:

•SDA

•SCL

• EIO0 (Transfer Status Line) is toggled indicating

that new data is available and checking whether

the host has already started data reading or not.

FIGURE 6-1:

APPLICATION CIRCUITRY

6.1

ESD Considerations

The MGC3X30 provides Electrostatic Discharge (ESD)

Voltage protection up to 2 kV (HBM). Additional ESD

countermeasures may be implemented individually to

meet application-specific requirements.

6.2

Power Noise Considerations

MGC3X30 filtering capacitors are included in the

reference design schematic (Please refer to Figure 6-2).

6.3

Irradiated High-Frequency Noise

In order to suppress irradiated high-frequency signals,

the five Rx channels of the chip are connected to the

electrodes via serial 10 k

 resistors, as close as

possible to MGC3X30. The 10 k

 resistor and the

MGC3X30 input capacitance are building a low-pass

filter with a corner frequency of 3 MHz. An Additional

ferrite bead is recommended to suppress the coupling

of RF noise to the Tx channel (e.g., 600

 at 100 MHz).

An additional ferrite bead is recommended to suppress

the coupling of RF noise to the Tx channel (e.g., 600



at 100 MHz).

6.4

Reference Schematic

(3.3V

VDD  3.465V)

The reference application schematic for the MGC3X30

is depicted below in Figure 6-2.

MGC3x30

Host

Controller

SDA0

SCL0

EIO0

MCLR

SDA

SCL

GPIO

SDA

SCL

Vcc

MCLR

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