10

MLC0xxB Series Technical Summary

MEGAWIN

Interrupt Vectors

Vector Address

Item

Priority

Properties

Memo

FFFCH, FFFDH

RESET

1

Ext.

Initial reset

FFFAH, FFFBH

NMI

2

Int./Ext.

Non-maskable interrupt vector

FFF8H, FFF9H

DIV0x

3

Int.

Selectable divider 0 carry out interrupt

FFF6H, FFF7H

TM0

4

Int.

Timer 0 overflow interrupt

FFF4H, FFF5H

P0

5

Ext.

Port P0 interrupt vector

FFF2H, FFF3H

TM1

6

Int.

Timer 1 overflow interrupt

FFF0H, FFF1H

TM2

7

Int.

Timer 2 overflow interrupt

FFEEH, FFEFH

DIV1x

8

Int.

Selectable divider 1 carry out interrupt

There are eight kinds of interrupt sources are provided in MLC0xxB series. The flag IRQ_EN and

IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the

corresponding bits of flag IRQ_EN has been set by software, an interrupt is generated. When an

interrupt occurs, all of the interrupts are inhibited until the CLI or STA IRQ_EN, #I instruction is

invoked. Executing the SEI instruction can also disable the interrupts.

Interrupt

Process

Logic

IRQ_EN.0

Interrupt

Vector

Generator

Logic

Initial Reset

STA IRQ_EN, #I

Enable

IRQ_ST.0

NMI_EV

Initial Reset

STA IRQ_CLR, #I

SEI instruction

Disable

Divider0

overflow signal

Timer0

underflow signal

Selectable

NMI

IRQ_EN.1

S

R

Q

S

R

Q

S

R

Q

IRQ_ST.1

IRQ_ST.5

IRQ_EN.5

S

R

Q

.

.

.

CLI instruction

FFFCH, FFFDH

FFFAH, FFFBH

FFF8H, FFF9H

FFF6H, FFF7H

FFF4H, FFF5H

FFF2H, FFF3H

FFF0H, FFF1H

FFEEH, FFEFH

NMI

Process

Logic

Divider1

overflow signal