PERICOMPI7C8150 datasheet(14/106 Pages) PERICOM

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PI7C8150

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

August 22, 2002 – Revision 1.02

2.2.2

SECONDARY BUS INTERFACE SIGNALS

Name

Pin #

Type

Description

S_AD[31:0]

206, 204, 203,

201, 200, 198,

197, 195, 192,

191, 189, 188,

186, 185, 183,

182, 165, 164,

162, 161, 159,

154, 152, 150,

147, 146, 144,

143, 141, 140,

138, 137

Secondary Address/Data: Multiplexed address and data

bus. Address is indicated by S_FRAME_L assertion.

Write data is stable and valid when S_IRDY_L is

asserted and read data is stable and valid when

S_IRDY_L is asserted. Data is transferred on rising

clock edges when both S_IRDY_L and S_TRDY_L are

asserted. During bus idle, PI7C8150 drives S_AD to a

valid logic level when S_GNT_L is asserted

respectively.

S_CBE[3:0]

194, 180, 167, 149

Secondary Command/Byte Enables: Multiplexed

command field and byte enable field. During address

phase, the initiator drives the transaction type on these

pins. The initiator then drives the byte enables during

data phases. During bus idle, PI7C8150 drives

S_CBE[3:0] to a valid logic level when the internal grant

is asserted.

S_PAR

168

Secondary Parity: Parity is even across S_AD[31:0],

S_CBE[3:0], and S_PAR (i.e. an even number of 1’s).

S_PAR is an input and is valid and stable one cycle after

the address phase (indicated by assertion of

S_FRAME_L) for address parity. For write data phases,

S_PAR is an input and is valid one clock after

S_IRDY_L is asserted. For read data phase, S_PAR is

an output and is valid one clock after S_TRDY_L is

asserted. Signal S_PAR is tri-stated one cycle after the

S_AD lines are tri-stated. During bus idle, PI7C8150

drives S_PAR to a valid logic level when the internal

grant is asserted.

S_FRAME_L

179

STS

Secondary FRAME (Active LOW): Driven by the

initiator of a transaction to indicate the beginning and

duration of an access. The de-assertion of S_FRAME_L

indicates the final data phase requested by the initiator.

Before being tri-stated, it is driven to a de-asserted state

for one cycle.

S_IRDY_L

177

STS

Secondary IRDY (Active LOW): Driven by the

initiator of a transaction to indicate its ability to

complete current data phase on the secondary side. Once

asserted in a data phase, it is not de-asserted until the end

of the data phase. Before tri-stated, it is driven to a de-

asserted state for one cycle.

S_TRDY_L

176

STS

Secondary TRDY (Active LOW): Driven by the target

of a transaction to indicate its ability to complete current

data phase on the secondary side. Once asserted in a

data phase, it is not de-asserted until the end of the data

phase. Before tri-stated, it is driven to a de-asserted state

for one cycle.

S_DEVSEL_L

175

STS

Secondary Device Select (Active LOW): Asserted by

the target indicating that the device is accepting the

transaction. As a master, PI7C8150 waits for the

assertion of this signal within 5 cycles of S_FRAME_L

assertion; otherwise, terminate with master abort. Before

tri-stated, it is driven to a de-asserted state for one cycle.

S_STOP_L

173

STS

Secondary STOP (Active LOW): Asserted by the

target indicating that the target is requesting the initiator

to stop the current transaction. Before tri-stated, it is

driven to a de-asserted state for one cycle.

S_LOCK_L

172

STS

Secondary LOCK (Active LOW): Asserted by the

master for multiple transactions to complete.

PERICOMPI7C8150 Datasheet(PDF) 14 Page - Pericom Semiconductor Corporation

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