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ISL68137IRAZ Datasheet(PDF) 13 Page - Intersil Corporation |
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ISL68137IRAZ Datasheet(HTML) 13 Page - Intersil Corporation |
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13 / 53 page ![]() ISL68137 13 FN8757.0 September 27, 2016 Submit Document Feedback Functional Description Overview The ISL68137 is a digital dual output 7-phase PWM controller that can be programmed for single output 7+0, dual output 6+1, 5+2, or 4+3 phase operation. Operation using less than 7 phases between 2 outputs is also supported. Existing digital multiphase solutions utilize analog comparator based schemes (nonlinear) to bolster the inadequate transient response common to many digital multiphase solutions. The ISL68137 uses a linear voltage regulation scheme to address transient loads. As a result, it is much easier for users to configure and validate their designs when compared with nonlinear schemes. By combining a proprietary low noise and zero latency digital current sense scheme with cutting edge digital design techniques, Intersil is able to meet transient demands without resorting to nonlinear schemes. In addition, the ISL68137 can store up to 8 user configurations in NVM and allows the user to select the desired configuration via pin-strap (CONFIG). The result is a system that is easy to configure and deploy. A number of performance enhancing features are supported in the ISL68137. These include AVSBus control, diode braking, automatic phase dropping, DCR/resistor/smart power stage current sense support, load line regulation and multiple temperature sensing options. To facilitate configuration development, the PowerNavigator™ GUI provides a step-by-step arrangement for setup and parametric adjustment. Once a configuration has been set, the user may employ PowerNavigator™ to monitor telemetry or use a direct PMBus interface based on the supported command set. PWM Modulation Scheme The ISL68137 uses Intersil's proprietary linear synthetic current modulation scheme to improve transient performance. This is a unique constant frequency, dual edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads. Current balance is an inherent part of the regulation scheme. The modulation scheme is capable of overlapping pulses should the load profile demand such operation. In addition, the modulator is capable of adding or removing pulses from a given cycle in response to regulation demands while still managing maximum average frequency to safe levels. For DC load conditions the operating frequency is constant. PMBus Address Selection When communicating with multiple PMBus devices on a single bus, each device must have its own unique address so the host can distinguish between the devices. The device address can be set using a 1% resistor on the SA pin according to the pin-strap options listed in Table 2. Phase Configuration The ISL68137 supports up to two regulated outputs through seven configurable phases. Either output is capable of controlling up to seven phases in any arbitrary mix. Phase assignments are accomplished via the PowerNavigator™ GUI. While the device supports arbitrary phase assignment, it is good practice to assign phases to Output 1 in descending sequential numerical order starting from Phase 6. For example, a 4-phase rail could consist of phases 6, 5, 4 and 3. For Output 0, phases would be assigned starting from Phase 0 in ascending sequential numerical order. Automatic Phase Add and Drop In order to produce the most optimal efficiency across a wide range of output loading, the modulator supports automatic dropping or adding of phases. Use of automatic phase dropping is optional. If automatic phase dropping is enabled, the number of active phases at any time is determined solely by load current. During operation, phases of Output 1 will drop beginning with the lowest phase number assigned. Phase dropping begins with the highest assigned phase number. Figure 8 illustrates the typical characteristic of efficiency vs load current vs phase count. TABLE 2. RESISTOR VALUES TO ADDRESS MAPPING R SA (Ω) PMBus ADDRESS R SA (Ω) PMBus ADDRESS 0 60h 1500 50h 180 61h 1800 51h 330 64h 2200 54h 470 65h 2700 55h 680 40h 3300 58h 820 41h 3900 59h 1000 44h 4700 5Ch 1200 45h 5600 5Dh LOAD (A) FIGURE 8. EFFICIENCY vs PHASE NUMBER I1 I2 I3 I4 I5 0 20 60 80 100 120 140 160 180 40 |
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