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LH155BA Datasheet(PDF) 41 Page - Sharp Corporation |
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LH155BA Datasheet(HTML) 41 Page - Sharp Corporation |
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41 / 51 page ![]() 41 LH155BA 7. ELECTRICAL CHARACTERISTICS 7.1. DC Characteristics (Unless otherwise specified, VSS = 0 V, VDD = +1.8 to +5.5 V, TOPR = –30 to +85 °C) PARAMETER SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Input "Low" voltage VIL D7-D0, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, OSCI, LP, FLM, M, SDA, SCL, P/S, RESB, EXA, PMODE 0 0.2VDD V Input "High" voltage VIH 0.8VDD VDD V Output "Low" voltage VOL IOL = 0.4 mA D7-D0, LP, FLM, M 0.4 V Output "High" voltage VOH IOH = –0.4 mA VDD – 0.4 V Input leakage current ILI VI = VSS or VDD CSB, RS, M/S, M86, RDB, WRB, CK, CKS, OSCI, SDA, SCL, P/S, RESB, EXA, PMODE –10 10 µA Output leakage current ILO VI = VSS or VDD D7-D0, LP, FLM, M –10 10 µA 1 LCD drive output ON resistance RON |∆VON| = 0.5 V V0 = 10 V SEG0-SEG127, COM0-COM63 4 k$ 2 V0 = 6 V Standby current ISTB CK = 0 V CSB = VDD VDD 20 µA 3 Supply current (1) IDD1 During sleep mode VDD 20 µA 4 Reset ("L") pulse width tRW RESB 10 µs NOTES : 1. Applied when D7 to D0, LP, FLM, and M are in the high impedance state. 2. Resistance when 0.5 V is applied between each output pin and each power supply (V0, V1, V2, V3, V4). Applied when power is supplied at power bias ratio of 1/9 in the external power supply mode. 3. Current at the VDD pin when the master clock stops, the chip is not selected (CSB = VDD), and no load is used. All circuits stop. 4. Sleep mode supply current. Stop internal oscillation clock, using external EXA signal. Without using booster circuits. Graphic and segment displays OFF. Icon display ON. No load. 5. Applied when no access is made by the MPU when the internal oscillation circuit (RF = 680 k$) and power supply circuit (PMODE = "L") are used. The electronic volume is preset (the code is "1 1 1 1"). The display is OFF and the LCD drive pin is not loaded. Measuring conditions : VDD = VEE, VR1 = VR2, C1 = C2 = 1 µF, R1 + R2 + R3 = 4 M$. 6. Active mode supply current. Using internal oscillation clock. Writing at fCYC the graphic display data which are reversed every one bit. No load. 7. Oscillation frequency when connecting a feedback resistor (RF) of 680 k$ between OSCI and OSCO. 6 VDD = 5 V VDD = 3 V VDD = 2 V 10 5 VDD = 5 V VDD = 3 V VDD = 2 V 10 5 80 120 VDD = 2 V VDD = 3 V VDD = 5 V 5 µA 240 VDD, VEE During hold mode IDD2 Supply current (2) Supply current (3) IDD3 During active mode fCYC = 100 kHz VDD 1 200 µA 6 VDD = 5 V VDD = 3 V VDD = 2 V 400 200 24 28 VDD = 2 V VDD = 3 V VDD = 5 V 7 kHz 30 OSCO RF = 680 k$±2% fOSC Oscillation frequency |
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