D2-71083-LR datasheet(21/32 Pages) INTERSIL

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D2-7xx83

FN7838.3

April 28, 2016

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Audio Output

PWM AUDIO AMPLIFIER OUTPUT

The D2-7xx83 family supports multiple PWM output topologies,

which enables system designs to use an output stage, which

meets the cost and performance requirements of the particular

application. Twelve PWM channels are mapped to 18 PWM

output pins by the programmed firmware. The PWM output pins

are 3.3V CMOS levels with either 8mA or 16mA drive capability.

Output topologies supported include:

• Half-bridge, N+N or N+P

• Full-bridge, N+N or N+P using 2-level modulation, 2 or

4-quadrant control

LINE LEVEL OUTPUT

In addition to amplified outputs, the D2-7xx83 family IC also

supports line-level outputs that generate a nominal 1VRMS

output using a simple passive filter.

Headphone outputs or line-level outputs that require a 2VRMS (or

higher output level) are also supported, using an active filter to

accomplish the signal level needs.

S/PDIF TRANSMITTER

The D2-7xx83 contains one IEC60958 compatible S/PDIF Digital

transmitter. The transmitter complies with the consumer

applications defined in IEC60958-3. The transmitter supports

24-bit audio data, 24-bit user data, and 30-bit channel status

data.

A bit-exact pass-through mode from the selected SPDIFRX[1:0]

input is also supported. This simplifies system designs that

require that the IEC61937-compliant original compressed audio

bitstream be made available at the back panel of the product, as

well as giving the user the capability to select a decoded (and

downmixed, if necessary) IEC60958-compliant stereo or mono

Linear PCM output for digital audio recording/playback

capabilities.

The D2-7xx83 family optional firmware offers digital audio

format conversion support for I2S Digital format input to S/PDIF

Digital format output, as well as S/PDIF Digital format input to

I2S Digital format output, for all digital audio Linear PCM

(non-compressed) audio sources. This functionality is not

available for compressed audio inputs, unless the compressed

audio data is first decoded by the internal DSP, and if necessary,

downmixed to 2 channels.

This format conversion path offers the ability to reduce the clock

jitter on the output due to the fact that both inputs (when in this

mode) pass through the professional-grade Sample-Rate Converters

(SRC). This approach also enables consumer products to output a

downsampled digital audio output for audio that may not otherwise

be made available to the consumer in the original higher-bandwidth

format due to certain consumer electronic/content protection

licensing restrictions.

SERIAL AUDIO OUTPUT

D2-7xx83 family IC-based systems support outputting a bit-exact

pass-through of a compressed audio bitstream, or a decoded,

down-mixed (Lt/Rt or Lo/Ro) and downsampled 2 channel Linear

PCM audio bitstream via a specified SAI port, or S/PDIF Digital

transmitter. In addition, depending on the firmware functionality,

it is possible for unused SAI (Serial Audio Interfaces) to also

support I2S output as well, in either slave or master mode. The

output audio sample rate is determined by the firmware and can

vary from 32kHz up to 192kHz.

HD Audio

HDA INTERFACE

The HD Audio interface also provides a control interface. This

control interface uses the HD Audio GPI, GPO, and GPIO 8-bit

ports to provide a message passing facility between the

D2-7xx83 and the PC.

The D2-7xx83 fully supports Windows® Hardware Quality Labs

(WHQL™)-certification as, it is a UAA-Compliant Secondary HD

Audio CODEC. The devices may be used either as the primary

HDA CODEC, or as the second HDA CODEC in the system.

Features supported are:

• Message passing to other devices located on the motherboard

(e.g. HP jack detection and reporting.)

• Amplifier firmware download.

• Amplifier code load during system boot.

• Amplifier control protocol (D2Audio Canvas II support).

HD AUDIO PLAY

The D2-7xx83 provides for direct connection of a PC’s HD Audio

(HDA) Controller to the device. In this configuration, the

D2-7xx83 functions as an HDA CODEC with powered (amplified)

outputs.

Supported Features Include:

• 2, 4, 6, or 8 Amplified or PWM DAC Channels

• Audio Sample Rates 48kHz, 96kHz, 192kHz

• Data Widths of 16-bit, 20-bit, and 24-bit

• Independent Channel Gain Control

The HDA interface uses 5 of the 6 pins of the SAI 3 port. The HDA

interface captures the audio streams and converts them into one

to four I2S data streams, depending on the number of channels

used. These I2S stereo streams are routed through SAI 3 and SAI

4 and then on to the Sample Rate Converter. The SRC will rate

lock to the HDA stream and remove any jitter while converting

the data to the output sample rate.

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