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STK501 Datasheet(PDF) 13 Page - ATMEL Corporation |
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STK501 Datasheet(HTML) 13 Page - ATMEL Corporation |
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13 / 29 page ![]() Using the STK501 Top Module AVR ® STK501 User Guide 2-7 2.5.1 A16 The A16 pin on the PORTG/AUX connector is connected to A16 (address pin 16) on the SRAM. ATmega103(L) and ATmega128(L) support up to 60 KB of external SRAM. The STK501 SRAM footprint is for a 128 KB SRAM. Implementing software control of the A16 line will increase the memory range from 64 KB to 128 KB. This line is pulled low by default, addressing the lower 64 KB of the SRAM. Figure 2-10. SRAM Block Schematic 2.5.2 SRAMEN The SRAMEN pin on the PORTG/AUX connector is connected to the Chip-enable (CE) pin of the SRAM. This signal controls if the SRAM should be enabled or not. To enable the SRAM, a low level should be applied to this pin. This pin is pulled high by default, through a 10 k Ω resistor. Figure 2-10 shows a simplified block schematic on how the SRAM interface is implemented. Figure 2-11 shows how to enable the SRAM by short- ing SRAMEN and GND on the PORTG/AUX connector using one of the supplied jumpers. This signal can also be controlled by software or by some external control logic. Table 2-1. Recommended SRAM Devices Manufacturer Part Number Supply Voltage (V) Package ISSI IS63LV1024-T 3.3 TSOP-II ISSI IS63LV1024-J 3.3 SOJ 300-mil ISSI IS63LV1024-K 3.3 SOJ 400-mil IDT IDT71124-Y 5.0 SOJ 400-mil IDT IDT71V124SA-TY 3.3 SOJ 300-mil IDT IDT71V124SA-Y 3.3 SOJ 400-mil IDT IDT71V124SA-PH 3.3 TSOP-II VTG PA6 PA7 PA5 PA4 PA3 PA2 PA1 PA0 PA6 PA7 PA5 PA4 PA3 PA2 PA1 PA0 PC6 PC7 PC5 PC4 PC3 PC2 PC1 PC0 OE WE CE SRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 10K x 12 LATCH LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D1 D2 D3 D4 D5 D6 D7 D0 AVR PORTA ALE (PG2) WR (PG0) RD (PG1) PORTC OE A6 A7 A5 A4 A3 A2 A1 A0 VTG A[7:0] A6 A4 A2 A0 A7 A5 A3 A1 A6 A4 A2 A0 A7 A5 A3 A1 From PORTG/AUX connector SRAMEN A16 RAM HIGH ADDRESS |
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