ACS8520 datasheet(26/150 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.01/October 2003 © Semtech Corp.

Page 26

www.semtech.com

ACS8520 SETS

reference switch, and maintain the current phase offset.

If PBO is disabled while the device is in the Locked mode,

there may be a phase shift on the output SEC clocks as

the DPLL locks back to 0 degrees phase error. The rate of

phase shift will depend on the programmed bandwidth.

Enabling PBO whilst in the Locked stated will also trigger

a PBO event.

PBO Phase Offset

In order to minimize the systematic (average) phase error

for PBO, a PBO Phase Offset can be programmed in

0.101 ns steps in the cnfg_phase_offset_pbo register,

Reg.72. The range of the programmable PBO phase offset

is restricted to ±1.4 ns. This can be used to eliminate an

accumulation of phase shifts in one direction.

Input to Output Phase Adjustment

When PBO is off (including Auto-PBO on phase transients),

such that the system always tries to align the outputs to

the inputs at the 0° position, there is a mechanism

provided in the ACS8520 for precise fine tuning of the

output phase position with respect to the input. This can

be used to compensate for circuit and board wiring

delays. The output phase can be adjusted in 6 ps steps up

to 200 ns in a positive or negative direction. The phase

adjustment actually changes the phase position of the

feedback clock so that the DPLL adjusts the output clock

phases to compensate. The rate of change of phase is

therefore related to the DPLL bandwidth. For the DPLL to

track large instant changes in phase, either Lock8k mode

should be on, or the coarse phase detector should be

enabled. Register cnfg_phase_offset at Reg. 70 and 71

controls the output phase, which is only used when Phase

Build-out is off (Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 =0).

Input Wander and Jitter Tolerance

The ACS8520 is compliant to the requirements of all

relevant standards, principally ITU Recommendation

G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244,

GR253, G812, G813 and ETS 300 462-5 (1997).

All reference clock inputs have a tight frequency tolerance

but a generous jitter tolerance. Pull-in, hold-in and pull-out

ranges are specified in Table 8. Minimum jitter tolerance

masks are specified in Figures 9 and 10, and Tables 8

and 10, respectively. The ACS8520 will tolerate wander

and jitter components greater than those shown in

Figure 9 and Figure 10, up to a limit determined by a

combination of the apparent long-term frequency offset

caused by wander and the eye-closure caused by jitter

(the input source will be rejected if the offset pushes the

frequency outside the hold-in range for long enough to be

detected, whilst the signal will also be rejected if the eye

closes sufficiently to affect the signal purity). Either the

Lock8k mode, or one of the extended phase capture

ranges should be engaged for high jitter tolerance

according to these masks.

All reference clock ports are monitored for quality,

including frequency offset and general activity. Single

short-term interruptions in selected reference clocks may

not cause re- arrangements, whilst longer interruptions,

or multiple, short-term interruptions, will cause re-

arrangements, as will frequency offsets which are

sufficiently large or sufficiently long to cause loss-of-lock

in the phase-locked loop. The failed reference source will

be removed from the priority table and declared as

unserviceable, until its perceived quality has been

restored to an acceptable level.

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