CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

3

POST OFFICE BOX 655303

Terminal Functions

NAME

NO.

I/O

DESCRIPTION

EN

1

I

(with 60-k

Ω pullup)

ENABLE: Enables or disables all outputs simultaneously.

EN=1: outputs on according to S0, S1, and S2 setting

EN=0: outputs Y[2:0] off (high impedance)

See Table 1 for details.

IN, IN

3, 4

I (differential)

Differential input clock: Input stage is sensitive and has a wide common-mode range.

Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML,

HSTL). Since the input is high impedance, it is recommended to terminate the PCB

transmission line before the input (e.g. with 100-

Ω across input). Input can also be driven by

single ended signal if the complementary input is tight to VBB. A more advanced scheme for

single-ended signal is given in the application section near the end of this document.

The inputs deploy an ESD structure protecting the inputs in case of an input voltage exceeding

the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs is possible and

must be prevented by limiting the input voltage < VDD.

NC

12

No connect. Leave this pin open or tie to ground

S0, S1, S2

18, 19,

24

I

(with 60-k

Ω pullup)

Select mode of operation: Defines the output configuration of Y[2:0]. See Table 1 for

configuration.

Y[2:0],

Y[2:0]

9, 10,

15, 16,

21, 22

O (LVPECL)

LVPECL clock outputs: These outputs provide low-skew copies of IN pair or down divided

copies of clock IN based on selected mode of operation S[2:0]; If an output is unused, the

output can simply be left open to save power and minimize noise impact to the remaining

outputs.

VBB

6

O

Bias voltage output can be used to bias unused complementary input IN for single ended input

signals.

The output voltage of VBB is VDD − 1.3 V. When driving a load, the output current drive is limited

to about 1.5 mA.

VSS

7, 13

Supply

Device ground

VDDPECL

2, 5

Supply

Supply voltage PECL input + internal logic

VDD [0−2]

8, 11, 14,

17,20,

23

Supply

PECL output supply voltage for output Y[0−2]: Each output can be disabled by pulling the

corresponding VDDx to GND.

CAUTION: In this mode, no voltage from outside may be forced, because internal diodes could

be forced in forward direction; Thus, it is recommended to disconnect the output if it is not being

used.