ML6652 datasheet(21/28 Pages) MICRO-LINEAR

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ML6652

January 2002

Preliminary Datasheet

CONTROL REGISTERS

Bit

Name

Description

R/W

Default

Power Down

Setting bit to 1 powers down all circuits and resets all

R/W

control logic. Register bits are not reset (except the management interface)

and new configuration data is not loaded

FOUTOFF

Setting bit to 1 turns off the output stage of the Fiber Optic

R/W

driver leaving the output pins in a high impedance state.

Setting bit to 1 creates the exact same results as a 0 input on FOUTOFF#

TPOUTOFF

Setting bit to 1 turns off the output stage of the twisted pair

R/W

line driver leaving the output pins in a high impedance state. Setting bit

to 1 creates exact same result as 0 input on TPOUTOFF#

LPBKTOTP

Setting bit to 1 directs TPINP (pin 10) and TPINN (pin 11)

R/W

to loop back to TPOUTP (pin 1) and TPOUTN (pin 3). Including

the PLL in the 100Mbps signal path is controlled by <31:10>,

PLLCPBK#

LPBKTOFO

Setting bit to 1 directs FOINP (pin 33) and FOINN (pin 32)

R/W

to loop back to IOUT (pin 21) and IOUT# (pin 22). Including the

PLL in the 100Mbps signal path is controlled by <31:10> PLLCPBK#.

PLLCPBK#

Setting bit to 1 removes the clock/data recovery PLL from

R/W

the signal path during 100Mbps loop back modes

7-4

Reserved

3-0

Reserved

Control Registers

ADVERTHD#

Setting bit to 1 AND TRANSPARENT# <30.11> set to 1

R/W

causes Half Duplex capability to be advertised in FLP bursts

Setting bit to 0 AND TRANSPARENT# <30.11> set to 1

causes Half Duplex capability to not be advertised in FLP bursts

Setting TRANSPARENT# <30.11> to 0 causes ADVERTHD#

to be ignored

DSBLAN

Setting bit to 1 disables detection of FLNP and FLP bursts

R/W

Set by

SPEED

(pin 27)

RESET

Setting this bit to 1 causes all configuration pins to be read

R/W

and all register bits to be initialized 3 to 8µs after the bit is

returned to a 0. The bit is self clearing

LIW

Setting this bit to 1 enables the Link Integrity Warning function

R/W

Set by

AD4LIW

(pin 4)

TRANSPARENT#

Setting bit to 1 enables NON-TRANSPARENT Mode of operation

R/W

Set by

Setting bit to 0 enables TRANSPARENT Mode of operation

DUPLEX

(pin 25)

ADVERTFD#

Setting bit to 0 and TRANSPARENT# <30.11> set to 1

R/W

Set by

causes Full Duplex capability to be advertised in FLP bursts

DUPLEX

Setting bits to 1 and TRANSPARENT# <30.11> set to 0

(pin 25)

causes Full Duplex capability to not be advertised in FLP bursts

Setting TRANSPARENT# <30.11> to 0 causes ADVERFTD#

to be ignored

Bit

Name

Description

R/W

Default

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