HMC701LP6CE datasheet(26/40 Pages) AD

26 / 40 page

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HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

High impedance always:

reg2h[1:0] = 10

reg1ah[13:12] = xx (x=don’t care)

Figure 18 LD/SDo output control

Serial Port WRITE Operation

aVDD = DVDD = 3V ±10%, aGnD = DGnD = 0V

Table 4. Timing Characteristics

Parameter

Conditions

Min.

Typ.

Max

Units

SEn to ScLK setup time

nsec

SDi to ScLK setup time

nsec

SDi to cLK hold time

nsec

ScLK high duration

nsec

ScLK low duration

nsec

SEn High duration

640

nsec

SEn low duration

nsec

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