CYIFS741

Document Number: 001-73430 Rev. *A

Page 13 of 19

Application Notes and Schematics

The schematic diagram shown below is a simple minimum component application example of an CYIFS741 design.

Figure 11. Simple minimum component application example of an CYIFS741 design [5]

Figure 12 is the equivalent internal oscillator circuit used in the

CYIFS741.

Figure 12. Equivalent oscillator circuit used in the CYIFS741

Calculating dB Reduction

The dB reduction for a given frequency and spread can be

calculated using a simple formula. This formula is only helpful in

determining a relative dB reduction for a given application. This

formula assumes an ideal clock with 50% duty cycle and

therefore only predicts the EMI reduction of odd harmonics.

Other circumstances such as non-ideal clock and noise will affect

the actual dB reduction. The formula is as follows;

dB = 6.5 + 9(Log10(F)) + 9(Log10(P))

Where; F = Frequency in MHz, P = total % spread (2.5% = 0.025)

Using a 50 MHz clock with a 2.5% spread, the theoretical dB

reduction would be;

dB @ 50 MHz (Fund) = 6.5 + 15.29 – 14.42 = 7.37

CYIFS741

Note