Data Sheet

HMC6301

Rev. A | Page 13 of 24

TIME = 0

ENABLE

CLK

1

01234567

012

34567

8

9 10 11 12 13 14 15 16 17

DATA

SCAN OUT

LSB

MSB LSB

MSB

LSB

MSB

LSB

MSB

WRITE DATA = (xxxxxxxx)

ARRAY ADDRESS

CHIP

ADDRESS

R/W = 0

27

READ DATA

Figure 18. Timing Diagram for Reading a Row of the Receiver Serial Interface

RECEIVER REGISTER ARRAY ASSIGNMENTS

All register arrays are read/write, unless otherwise noted.

Table 6. Receiver Register Array Assignments

Register Array

Row, Bit

Internal Signal Name

Signal Function

ROW0

ROW0, Bit 7

lna_pwrdwn

Active high to power down the LNA.

ROW0, Bit 6

bbamp_pwrdn_i

Active high to power down the baseband I channel.

ROW0, Bit 5

bbamp_pwrdn_q

Active high to power down the baseband Q channel.

ROW0, Bit 4

divider_pwrdn

Active high to power down the LO divider.

ROW0, Bit 3

mixer_pwrdn

Active high to power down the RF mixer.

ROW0, Bit 2

ifmixer_pwrdn/ifmixer_pwrd

n_i

Active high to power down the I channel IF mixer.

ROW0, Bit 1

tripler_pwrdn

Active high to power down the LO tripler.

ROW0, Bit 0

ifvga_pwrdn

Active high to power down the IF VGA.

ROW1

ROW1, Bit 7

ipc_pwrdwn

Active high to power down on-chip current reference generator.

ROW1, Bit 6

ifmix_pwrdn_q

Active high to power down the Q channel IF mixer.

ROW1, Bit 5

if_bgmux_pwrdn

Active high to power down one of the three on-chip band gap references (IF) and

associated mux.

ROW1, Bit 4

ask_pwrdn

Active high to power down the ASK demodulator.

ROW1, Bit 3

bbamp_atten1_0

Controls first baseband attenuator; ROW1, Bits[2:3].

11 is 18 dB attenuation.

10 is 12 dB attenuation.

01 is 6 dB attenuation.

00 is 0 dB attenuation.

ROW1, Bit 2

bbamp_atten1_1

ROW1, Bit 1

bbamp_sell_ask

Active high to multiplex the AM detector output into the I channel baseband amplifier

input.

ROW1, Bit 0

bbamp_sigshort

Active high to short the input to the I and Q channel baseband amplifiers.