WM8776 datasheet(21/55 Pages) WOLFSON

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WM8776

PP Rev 1.91 June 2004

The MSB of the left channel ADC data is output on DOUT and changes on the same falling

edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising

edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data

(Figure 18).

ADCLRC

ADCBCLK

DOUT

Word Length (WL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 18 DSP Late Mode Timing Diagram – ADC Data Output

In both early and late DSP modes, the left channel is always sent first, followed immediately

by the right channel. No DACBCLK edges are allowed between the data words.

CONTROL INTERFACE OPERATION

The WM8776 is controlled by writing to registers through a serial control interface. A control

word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control

bits in each control register. The control interface can operate as either a 3-wire or 2-wire

MPU interface. The MODE pin selects the interface format, as shown in Table 10. .

MODE

Control Mode

2 wire interface

3 wire interface

Table 10 Control Interface Selection via MODE Pin

The control interface is 5V tolerant, meaning that the control interface input signals CE, CL

and DI as well as MODE may have an input high level of 5V while DVDD is 3V. Input

thresholds are determined by DVDD.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

In 3-wire mode, every rising edge of CL clocks in one data bit from the DI pin. A rising edge

on CE latches in a complete control word consisting of the last 16 bits. The 3-wire interface

protocol is shown in Figure 19.

Figure 19 3-wire SPI Compatible Interface

B15

B14

B13

B12

B11

B10

control register address

control register data bits

latch

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