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WM9713 Datasheet(PDF) 82 Page - Wolfson Microelectronics plc |
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WM9713 Datasheet(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 111 page ![]() WM9713L Preliminary Technical Data 1 PTD, March 2004, Rev 2.2 82 Table 65 Extended Power Down Register (2) (Additional to AC’97 Rev 2.2) Note: 1. When disabling a PGA, always ensure that it is muted first. ADDITIONAL POWER MANAGEMENT Mixer output inverters: see “Mixer output Inverters” section. Inverters are OFF by default. Touchpanel Interface: see “Controlling the Touchpanel Digitiser / Power Management”. The touchpanel digitiser is OFF by default. SLEEP MODE Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9713L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits. For example, the low-power standby mode described below is a sleep mode. It is desirable to use sleep modes whenever possible, as this will save power. The following functions do not require a clock and can therefore operate in sleep mode: • Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode • Pen-down detection • GPIO and interrupts • Battery alarm / analogue comparators The WM9713L can awake from sleep mode as a result of • A warm reset on the AC-Link (according to the AC’97 specification) • A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see “GPIO and Interrupt Control” section) • A virtual GPIO event such as pen-down, battery alarm, etc. (see “GPIO and Interrupt Control” section) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 15 MCD 1 (OFF) Disables microphone current detect 14 MICBIA S 1 (OFF) Disables microphone bias 13 MONO 1 (OFF) Disables MONO output PGA (see Note 1) 12 OUT4 1 (OFF) Disables OUT4 output PGA ( “ “ ) 11 OUT3 1 (OFF) Disables OUT3 output PGA ( “ “ ) 10 HPL 1 (OFF) Disables HPL output PGA ( “ “ ) 9 HPR 1 (OFF) Disables HPR output PGA ( “ “ ) 8 SPKL 1 (OFF) Disables SPKL output PGA ( “ “ ) 7 SPKR 1 (OFF) Disables SPKR output PGA ( “ “ ) 6 LL 1 (OFF) Disables LINEL PGA ( “ “ ) 5 LR 1 (OFF) Disables LINER PGA ( “ “ ) 4 MOIN 1 (OFF) Disables MONOIN PGA ( “ “ ) 3 MA 1 (OFF) Disables mic PGA MA ( “ “ ) 2 MB 1 (OFF) Disables mic PGA MB ( “ “ ) 1 MPA 1 (OFF) Disables mic pre-amp MPA 3Eh Powerdown (2) 0 MPB 1 (OFF) Disables mic pre-amp MPB Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. |
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