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DS2196LN Datasheet(PDF) 98 Page - Dallas Semiconductor

Part # DS2196LN
Description  T1 Dual Framer LIU
PDF  157 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2196LN Datasheet(HTML) 98 Page - Dallas Semiconductor

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Table 16-1: Error Rate Options
ER3
ER2
ER1
ER0
Error Rate
0000
No errors inserted
0001
1 in 16
0010
1 in 32
0011
1 in 64
0100
1 in 128
0101
1 in 256
0110
1 in 512
0111
1 in 1024
1000
1 in 2048
1001
1 in 4096
1010
1 in 8192
1011
1 in 16384
1100
1 in 32768
1101
1 in 65536
1110
1 in 131072
1111
1 in 262144
NOE1A: NUMBER of ERRORS 1 FRAMER A (Address = 81 Hex)
NOE1B: NUMBER of ERRORS 1 FRAMER B (Address = 86 Hex)
NOE2A: NUMBER of ERRORS 2 FRAMER A (Address = 82 Hex)
NOE2B: NUMBER of ERRORS 2 FRAMER B (Address = 87 Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
NOE1
––––––
C9
C8
NOE2
SYMBOL
POSITION
NAME AND DESCRIPTION
C9
NOE2.1
MSB of the 10–bit Number of Errors Counter
C0
NOE1.0
LSB of the 10–bit Number of Errors Counter
Number Of Errors Registers.
The Number Of Error registers determines how many errors will be
generated. Up to 1023 errors can be generated. The Host will load the number of errors to be generated
into the NOE registers. The Host can also update the number of errors to be created by first loading the
prescribed value into the NOE registers and then toggling the WNOE bit in the Error Rate Control
registers. Refer to Table 16-2 for examples.



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