AT43USB370E-AC datasheet(9/50 Pages) ATMEL

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AT43USB370

3340B–USB–12/03

Reset

The reset signal to the AT43USB370 is active low. On reset, both the USBC and SIC are ini-

tialized and the System Processor Interface Registers are restored to their default values.

Figure 4 shows the Reset timing diagram. For Reset timing, see Table 5 on page 47.

Figure 4. Reset Timing

Power Supply

The AT43USB370 requires an external supply of 3.3 V and 1.8 V.

Firmware

Download

Mechanism

The AT43USB370 provides an in-system programming of the USBC and the SIC through the

external system processor. Programming requires SELECT, PROG, READY and DONE con-

trol signals. These control I/Os are dedicated to in-system firmware download and are not

used during normal operation.

The firmware is downloaded in the program memories (SRAM) of the internal controllers after

power-up or reset. The SELECT signal is used to select the USBC or the SIC for program-

ming. The PROG signal is used to mark the start and end of firmware download. The READY

and DONE signals are used for handshaking during successive programming write cycles.

The programming sequence of an internal controller is described as follows:

One of the controllers is selected using the SELECT pin of the AT43USB370. Logic low

selects the USBC and logic high selects the SIC. The order of programming of the con-

trollers is immaterial. Any of the controllers can be programmed first.

The PROG pin is asserted high by the system processor to indicate the start of

programming.

The system processor writes to a dummy address (anywhere in the AT43USB370

addressable space of the memory mapping) to assert CS_N and WE_N to

AT43USB370.

The system processor writes the 32-bit program word on the data bus.

The system processor waits for READY to be asserted high by the AT43USB370.

AT43USB370 asserts READY logic high to signal to the system processor that the

32-bit data word has been written to the program memory of the selected controller.

The system processor asserts the DONE signal high after detecting logic high on

READY

AT43USB370 asserts READY logic low.

The system processor asserts logic low on DONE.

10. This completes one 32-bit write cycle of the controller's programming. Steps 2 to 8

repeated until the entire firmware is downloaded in the program memory of the

selected controller.

11. Step 1 is then repeated to select the remaining controller. Step 2 to 9 are repeated to

program the remaining controller.

12. The PROG is de-asserted by the system processor once the firmware download is

complete. This signals an end of in-system programming of the AT43USB370.

The 32-bit word written by the system processor to its system bus must conform to the follow-

ing format:

•

Bits15:0: Address of the instruction

RESET_N

AT43USB370E-AC Datasheet(PDF) 9 Page - ATMEL Corporation

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