DS21552LN datasheet(99/137 Pages) DALLAS

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19.2 TAP CONTROLLER STATE MACHINE

The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of

JTCLK. See Figure 19-1.

TEST-LOGIC-RESET

Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will

contain the IDCODE instruction. All system logic of the device will operate normally.

RUN-TEST-IDLE

The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and

test registers will remain idle.

SELECT-DR-SCAN

All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the

controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge

on JTCLK moves the controller to the Select-IR-Scan state.

CAPTURE-DR

Data may be parallel-loaded into the test data registers selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the test

DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.

SHIFT-DR

The test data register selected by the current instruction will be connected between JTDI and JTDO and

will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected

by the current instruction is not placed in the serial path, it will maintain its previous state.

EXIT1-DR

While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which

terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put

the controller in the Pause-DR state.

PAUSE-DR

Shifting of the test registers is halted while in this state. All test registers selected by the current

instruction will retain their previous state. The controller will remain in this state while JTMS is LOW.

A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state.

EXIT2-DR

A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR

state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-

DR state.

UPDATE-DR

A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of

the test registers into the data output latches. This prevents changes at the parallel output due to changes

in the shift register.

DS21552LN Datasheet(PDF) 99 Page - Dallas Semiconductor