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LMD18201 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LMD18201
Description  3A, 55V H-Bridge
PDF  8 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMD18201 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Supply Voltage (V
S, Pin 6)
60V
Voltage at Pins 3, 4, 5 and 9
12V
Voltage at Bootstrap Pins (Pins 1 and 11)
V
OUT + 16V
Peak Output Current (200 ms)
6A
Continuous Output Current (Note 2)
3A
Power Dissipation (Note 3)
25W
Sense Voltage (Pin 7 to Pin 8)
+0.5V to −1.0V
Power Dissipation (T
A = 25˚C, Free Air)
3W
Junction Temperature, T
J(max)
150˚C
ESD Susceptibility (Note 4)
1500V
Storage Temperature, T
STG
−40˚C to +150˚C
Lead Temperature (Soldering, 10 sec.)
300˚C
Operating Ratings(Note 1)
Junction Temperature, T
J
−40˚C to +125˚C
V
S Supply Voltage
+12V to +55V
Electrical Characteristics(Note 5)
The following specifications apply for V
S = 42V, unless otherwise specified. Boldface limits apply over the entire operating
temperature range, −40˚C
≤ T
J ≤ +125˚C, all other limits are for TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typ
Limit
Units
R
DS(ON)
Switch ON Resistance
Output Current = 3A (Note 6)
0.33
0.4/0.6
Ω (max)
R
DS(ON)
Switch ON Resistance
Output Current = 6A (Note 6)
0.33
0.4/0.6
Ω (max)
V
CLAMP
Clamp Diode Forward Drop
Clamp Current = 3A (Note 6)
1.2
1.5
V (max)
V
IL
Logic Low Input Voltage
Pins 3, 4, 5
−0.1
V (min)
0.8
V (max)
I
IL
Logic Low Input Current
V
IN = −0.1V, Pins = 3, 4, 5
−10
µA (max)
V
IH
Logic High Input Voltage
Pins 3, 4, 5
2
V (min)
12
V (max)
I
IL
Logic High Input Current
V
IN = 12V, Pins = 3, 4, 5
10
µA (max)
Undervoltage Lockout
Outputs Turn OFF
9
V (min)
11
V (max)
T
JW
Warning Flag Temperature
Pin 9
≤ 0.8V, I
L = 2 mA
145
˚C
V
F(ON)
Flag Output Saturation Voltage
T
J = TJW,IL = 2 mA
0.15
V
I
F(OFF)
Flag Output Leakage
V
F = 12V
0.2
10
µA (max)
T
JSD
Shutdown Temperature
Outputs Turn OFF
170
˚C
I
S
Quiescent Supply Current
All Logic Inputs Low
13
25
mA (max)
t
D(ON)
Output Turn-On Delay Time
Sourcing Outputs, I
OUT = 3A
300
ns
Sinking Outputs, I
OUT = 3A
300
ns
t
ON
Output Turn-On Switching Time
Bootstrap Capacitor = 10 nF
Sourcing Outputs, I
OUT = 3A
100
ns
Sinking Outputs, I
OUT = 3A
80
ns
t
D(OFF)
Output Turn-Off Delay Times
Sourcing Outputs, I
OUT = 3A
200
ns
Sinking Outputs, I
OUT = 3A
200
ns
t
OFF
Output Turn-Off Switching Times
Bootstrap Capacitor = 10 nF
Sourcing Outputs, I
OUT = 3A
75
ns
Sinking Outputs, I
OUT = 3A
70
ns
t
PW
Minimum Input Pulse Width
Pins 3, 4 and 5
1
µs
t
CPR
Charge Pump Rise Time
No Bootstrap Capacitor
20
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 2: See Application Information for details regarding current limiting.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is a function of TJ(max), θJA, and TA. The maximum allowable power dissi-
pation at any temperature is PD(max) = (TJ(max) −TA)/θJA, or the number given in the Absolute Ratings, whichever is lower. The typical thermal resistance from junction
to case (
θJC) is 1.0˚C/W and from junction to ambient (θJA) is 30˚C/W. For guaranteed operation TJ(max) = 125˚C.
Note 4: Human-body model, 100 pF discharged through a 1.5 k
Ω resistor. Except Bootstrap pins (pins 1 and 11) which are protected to 1000V of ESD.
Note 5: All limits are 100% production tested at 25˚C. Temperature extreme limits are guaranteed via correlation using accepted SQC (Statistical Quality Control)
methods. All limits are used to calculate AOQL, (Average Outgoing Quality Level).
Note 6: Output currents are pulsed (tW < 2 ms, Duty Cycle < 5%).
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