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LMF100CIWM Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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LMF100CIWM Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 28 page  LMF100 High Performance Dual Switched Capacitor Filter General Description The LMF100 consists of two independent general purpose high performance switched capacitor filters. With an external clock and 2 to 4 resistors, various second-order and first-order filtering functions can be realized by each filter block. Each block has 3 outputs. One output can be config- ured to perform either an allpass, highpass, or notch func- tion. The other two outputs perform bandpass and lowpass functions. The center frequency of each filter stage is tuned by using an external clock or a combination of a clock and re- sistor ratio. Up to a 4th-order biquadratic function can be re- alized with a single LMF100. Higher order filters are imple- mented by simply cascading additional packages, and all the classical filters (such as Butterworth, Bessel, Elliptic, and Chebyshev) can be realized. The LMF100 is fabricated on National Semiconductor’s high performance analog silicon gate CMOS process, LMCMOS™. This allows for the production of a very low off- set, high frequency filter building block. The LMF100 is pin-compatible with the industry standard MF10, but pro- vides greatly improved performance. Features n Wide 4V to 15V power supply range n Operation up to 100 kHz n Low offset voltage: typically (50:1 or 100:1 mode): Vos1 = ±5mV Vos2 = ±15 mV Vos3 = ±15 mV n Low crosstalk −60 dB n Clock to center frequency ratio accuracy ±0.2% typical n f0 x Q range up to 1.8 MHz n Pin-compatible with MF10 4th Order 100 kHz Butterworth Lowpass Filter Connection Diagram LMCMOS™ is a trademark of National Semiconductor Corporation. DS005645-2 DS005645-3 Surface Mount and Dual-In-Line Package DS005645-18 Top View Order Number LMF100CCN or LMF100CIWM See NS Package Number N20A or M20B July 1999 © 1999 National Semiconductor Corporation DS005645 www.national.com |
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