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FDC37C93XAPM Datasheet(PDF) 86 Page - SMSC Corporation |
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FDC37C93XAPM Datasheet(HTML) 86 Page - SMSC Corporation |
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86 / 280 page  86 PARALLEL PORT The FDC37C93xAPM incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The FDC37C93xAPM also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power- up. The functionality of the parallel port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the parallel port is shown below: DATA PORT BASE ADDRESS + 00H STATUS PORT BASE ADDRESS + 01H CONTROL PORT BASE ADDRESS + 02H EPP ADDR PORT BASE ADDRESS + 03H EPP DATA PORT 0 BASE ADDRESS + 04H EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H The bit map of these registers is: D0 D1 D2 D3 D4 D5 D6 D7 Note DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1 STATUS PORT TMOUT 0 0 nERR SLCT PE nACK nBUSY 1 CONTROL PORT STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1 EPP ADDR PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 AD7 2,3 EPP DATA PORT 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 EPP DATA PORT 1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 EPP DATA PORT 2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 EPP DATA PORT 3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus. |
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