LPC47M172 datasheet(49/227 Pages) SMSC

49 / 227 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 49

SMSC LPC47M172

DATASHEET

BITS 0 – 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the

individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps

after a hardware reset.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BITS 4 – 6 UNDEFINED

Always read as a logic “0”

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the

value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime

6.4.11 Configuration Control Register (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

DRATE

SEL1

DRATE

SEL0

RESET

COND.

N/A

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.

BIT 2 – 7 RESERVED

Should be set to a logical “0”

PS/2 Model 30 Mode

NOPREC DRATE

SEL1

DRATE

SEL0

RESET

COND.

N/A

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in

Model 30 register mode. Unaffected by software reset.

LPC47M172 Datasheet(PDF) 49 Page - SMSC Corporation

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