LMX2335TM datasheet(13/18 Pages) NSC

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Application Information (Continued)

Loop Gain Equations

A linear control system model of the phase feedback for a

PLL in the locked state is shown in

Figure 2 . The open loop

gain is the product of the phase comparator gain (Kφ), the

VCO gain (K

VCO/s), and the loop filter gain Z(s) divided by

the gain of the feedback counter modulus (N). The passive

loop filter configuration used is displayed in

Figure 3 , while

the complex impedance of the filter is given in

Equation (2).

(1)

(2)

The time constants which determine the pole and zero fre-

quencies of the filter transfer function can be defined as

(3)

T2 = R2

• C2

(4)

The 3rd order PLL Open Loop Gain can be calculated in

terms of frequency,

ω, the filter time contants T1 and T2, and

the design constants K

φ,K

VCO, and N.

(5)

From

Equation (3) we can see that the phase term will be de-

pendent on the single pole and zero such that the phase

margin is determined in

Equation (5).

φ(ω) = tan−1 (ω • T2) −tan−1 (ω • T1) + 180˚C

(6)

A plot of the magnitude and phase of G(s) H(s) for a stable

loop, is shown in

Figure 4 with a solid trace. The parameter

p shows the amount of phase margin that exists at the point

the gain drops below zero (the cutoff frequency wp of the

loop). In a critically damped system, the amount of phase

margin would be approximately 45 degrees.

If we were now to redefine the cut off frequency, wp’, as

double the frequency which gave us our original loop band-

width, wp, the loop response time would be approximately

halved. Because the filter attenuation at the comparison fre-

quency also diminishes, the spurs would have increased by

approximately 6 dB. In the proposed Fastlock scheme, the

higher spur levels and wider loop filter conditions would exist

only during the initial lock-on phase — just long enough to

reap the benefits of locking faster. The objective would be to

open up the loop bandwidth but not introduce any additional

complications or compromises related to our original design

criteria. We would ideally like to momentarily shift the curve

Figure 4 over to a different cutoff frequency, illustrated by

dotted line, without affecting the relative open loop gain and

phase relationships. To maintain the same gain/phase rela-

tionship at twice the original cutoff frequency, other terms in

the gain and phase

Equations (5), (6) will have to compen-

sate by the corresponding “1/w” or “1/w

2” factor. Examination

Equations (3), (4), (5) indicates the damping resistor vari-

able R2 could be chosen to compensate with “w” terms for

the phase margin. This implies that another resistor of equal

value to R2 will need to be switched in parallel with R2 during

the initial lock period. We must also ensure that the magni-

tude of the open loop gain, H(s)G(s) is equal to zero at wp’ =

2 wp. K

VCO,Kφ, N, or the net product of these terms can be

changed by a factor of 4, to counteract with w

2 term present

in the denominator of

Equations (3), (4). The K

φ term was

chosen to complete the transformation because it can

readily be switched between 1X and 4X values. This is ac-

complished by increasing the charge pump output current

from 1 mA in the standard mode to 4 mA in Fastlock.

Fastlock Circuit Implementation

A diagram of the Fastlock scheme as implemented in Na-

tional Semiconductors LMX2335/36/37 PLL is shown in

Fig-

ure 5. When a new frequency is loaded, and the RF1 I

CPo bit

is set high, the charge pump circuit receives an input to de-

liver 4 times the normal current per unit phase error while an

open drain NMOS on chip device switches in a second R2

resistor element to ground. The user calculates the loop filter

component values for the normal steady state consider-

ations. The device configuration ensures that as long as a

second identical damping resistor is wired in appropriately,

the loop will lock faster without any additional stability con-

siderations to account for. Once locked on the correct fre-

quency, the user can return the PLL to standard low noise

operation by sending a MICROWIRE instruction with the

RF1 I

CPo bit set low. This transition does not affect the

charge on the loop filter capacitors and is enacted synchro-

nous with the charge pump output. This creates a nearly

seamless change between Fastlock and standard mode.

DS012332-14

FIGURE 2. PLL Linear Model

DS012332-13

FIGURE 3. Passive Loop Filter

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