ADC10832CIWM datasheet(24/30 Pages) NSC

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Applications Hints (Continued)

34 Optional Adjustments

341 Zero Error

The zero error of the AD converter relates to the location

of the first riser of the transfer function (see

Figure 1 ) and

can be measured by grounding the minus input and applying

a small magnitude voltage to the plus input Zero error is the

difference between actual DC input voltage which is neces-

sary to just cause an output digital code transition from

000 0000 0000 to 000 0000 0001 and the ideal

LSB value

(

LSB e 20 mV for VREF ea 4096V)

The zero error of the AD does not require adjustment If

the minimum analog input voltage value VIN(Min) is not

ground the effective ‘‘zero’’ voltage can be adjusted to a

convenient value The converter can be made to output an

all zeros digital code for this minimum input voltage by bias-

ing any minus input to VIN(Min) This is useful for either the

differential or pseudo-differential input channel configura-

tions

342 Full-Scale

The full-scale adjustment can be made by applying a differ-

ential input voltage which is 1

LSB down from the desired

analog full-scale voltage range and then adjusting the VREF

voltage (VREF e VREFa –VREFb) for a digital output code

changing from 011 1111 1110 to 011 1111 1111 In bipolar

signed operation this only adjusts the positive full scale er-

ror

343 Adjusting for an Arbitrary Analog Input

Voltage Range

If the analog zero voltage of the AD is shifted away from

ground (for example to accommodate an analog input sig-

nal which does not go to ground) this new zero reference

should be properly adjusted first A plus input voltage which

equals this desired zero reference plus

LSB is applied to

selected plus input and the zero reference voltage at the

corresponding minus input should then be adjusted to just

obtain the 000 0000 0000 to 000 0000 0001 code transition

The full-scale adjustment should be made with the proper

minus input voltage applied by forcing a voltage to the plus

input which is given by

VIN(a)fs adj e VMAX b 15

(VMAX b VMIN)

(

where VMAX equals the high end of the analog input range

VMIN equals the low end (the offset zero) of the analog

range Both VMAX and VMIN are ground referred The VREF

(VREF e VREFa b VREFb) voltage is then adjusted to pro-

vide a code change from 011 1111 1110 to 011 1111 1111

Note when using a pseudo-differential or differential multi-

plexer mode where VREFa and VREFb are placed within

the Va and GND range the individual values of VREF and

VREFb do not matter only the difference sets the analog

input voltage span This completes the adjustment proce-

dure

35 The Input Sample and Hold

The ADC10831248’s samplehold capacitor is imple-

mented in the capacitor array After the channel address is

loaded the array is switched to sample the selected positive

analog input The sampling period for the assigned positive

input is maintained for the duration of the acquisition time

(tA) 45 clock cycles

This acquisition window of 45 clock cycles is available to

allow the voltage on the capacitor array to settle to the posi-

tive analog input voltage Any change in the analog voltage

on a selected positive input before or after the acquisition

window will not effect the AD conversion result

In the simplest case the array’s acquisition time is deter-

mined by the RON (3 kX) of the multiplexer switches the

stray input capacitance CS1 (35 pF) and the total array (CL)

and stray (CS2) capacitance (48 pF) For a large source

resistance the analog input can be modeled as an RC net-

work as shown in

Figure 14 The values shown yield an

acquisition time of about 11 ms for 10-bit unipolar or 10-bit

plus sign accuracy with a zero-to-full-scale change in the

input voltage External source resistance and capacitance

will lengthen the acquisition time and should be accounted

for Slowing the clock will lengthen the acquisition time

thereby allowing a larger external source resistance

TLH11391 – 29

FIGURE 14 Analog Input Model

The signal-to-noise ratio of an ideal AD is the ratio of the

RMS value of the full scale input signal amplitude to the

value of the total error amplitude (including noise) caused

by the transfer function of the ideal AD An ideal 10-bit plus

sign AD converter with a total unadjusted error of 0 LSB

would have a signal-to-(noise a distortion) ratio of about 68

dB which can be derived from the equation

S(N a D) e 602(n) a 18

where S(N a D) is in dB and n is the number of bits

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