M24C64-W datasheet(12/26 Pages) STMICROELECTRONICS

12 / 26 page

M24C64, M24C32

12/26

Figure 10. Read Mode Sequences

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

After the successful completion of a Read opera-

tion, the device’s internal address counter is incre-

mented by one, to point to the next byte address.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 10.) but

without sending a Stop condition.

Then, the bus master sends another Start condi-

tion, and repeats the Device Select Code, with the

Read/Write bit (RW) set to 1. The device acknowl-

edges this, and outputs the contents of the ad-

dressed

byte.

The

bus

master

must

not

acknowledge the byte, and terminates the transfer

with a Stop condition.

Current Address Read

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the Read/Write bit (RW) set

to 1. The device acknowledges this, and outputs

the byte addressed by the internal address

counter. The counter is then incremented. The bus

master terminates the transfer with a Stop condi-

tion, as shown in Figure 10.,

without acknowledg-

ing the byte.

DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

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